S71GS128NB0 SPANSION [SPANSION], S71GS128NB0 Datasheet - Page 122
S71GS128NB0
Manufacturer Part Number
S71GS128NB0
Description
128N based MCPs
Manufacturer
SPANSION [SPANSION]
Datasheet
1.S71GS128NB0.pdf
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122
A/DQ[15:0]
A/DQ[15:0]
A/DQ[15:0]
A[21:0]
ADV#
CLK
Refresh Configuration Register
V IH
V IL
V IH
V IH
V OH
V OL
V OH
V OL
V OH
V IL
V IL
V OL
Operating Mode (BCR[15]): Default = Asynchronous Operation
The operating mode bit selects either synchronous burst operation or the default
asynchronous mode of operation.
The refresh configuration register (RCR) defines how the CellularRAM device per-
forms its transparent self refresh. Altering the refresh parameters can
dramatically reduce current consumption during standby mode. Page mode con-
trol is also embedded into the RCR.
in the RCR. At power-up, the RCR is set to 0070h. The RCR is accessed using CRE
and A[19] LOW.
Figure 36. Latency Counter (Variable Initial Latency, No Refresh Collision)
Valid Address
Code 2
Code 3
Code 4
(Default)
A d v a n c e
CellularRAM Type 2
Table 22
Output
Valid
below describes the control bits used
I n f o r m a t i o n
Output
Output
Valid
Valid
Output
Output
Output
Valid
Valid
Valid
Legend:
cellRAM_00_A0 October 4, 2004
Output
Output
Output
Don't care
Valid
Valid
Valid
Output
Output
Output
Valid
Valid
Valid
Undefined
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