S71GS128NB0 SPANSION [SPANSION], S71GS128NB0 Datasheet - Page 158

• Manufacturer Part Number: S71GS128NB0
• Description: 128N based MCPs
• Manufacturer: SPANSION [SPANSION]

DQ[15:0]
LB#/UB#
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. To allow self-refresh operations to occur between transactions, CE# must remain HIGH for at least 5ns (t
158
A[22:0]
ADV#
WAIT
WE#
CE#
OE#
CLK
schedule the appropriate internal refresh operation. CE# can stay LOW between burst READ and burst WRITE
operations. See
LOW time (t
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V OH
V OL
V IH
V IL
Symbol
t
t
t
ACLK
BOE
CLK
High-Z
Symbol
t
t
t
CBPH
t
t
CLK
CSP
HD
SP
t CSP
t SP
t SP
t SP
Table 50. WRITE Timing Parameters—Burst WRITE Followed by Burst READ
CEM
Address
High-Z
Table 51. READ Timing Parameters—Burst WRITE Followed by Burst READ
Valid
t HD
t HD
t HD
).
“How Extended Timings Impact CellularRAM™ Operation”
12.5
Min
9
t CLK
Figure 54. Burst WRITE Followed by Burst READ
70ns/80 MHz
t SP
t SP
D[0]
t HD
12.5
t HD
Min
5
4
2
3
D[1]
70ns/80 MHz
A d v a n c e
Max
20
D[2]
CellularRAM Type 2
D[3]
t HD
Max
20
20
(Note 2)
t CBPH
I n f o r m a t i o n
t CSP
V OH
V OL
t SP
t SP
t SP
Address
Valid
Min
11
15
t HD
High-Z
t HD
t HD
85ns/66 MHz
Min
15
5
5
2
3
for restrictions on the maximum CE#
85ns/66 MHz
t BOE
t ACLK
Output
Valid
Max
20
ns
t KOH
Output
Max
Valid
20
20
Legend:
cellRAM_00_A0 October 4, 2004
Output
Valid
Don't Care
Output
Valid
Units
ns
ns
Units
ns
ns
ns
ns
ns
CBPH
t OHZ
High-Z
Undefined
) to