S71GS128NB0 SPANSION [SPANSION], S71GS128NB0 Datasheet - Page 117

• Manufacturer Part Number: S71GS128NB0
• Description: 128N based MCPs
• Manufacturer: SPANSION [SPANSION]

Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. A[19] = LOW to load RCR; A[19] = HIGH to load BCR.
3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored—additional WAIT cycles caused
October 4, 2004 cellRAM_00_A0
(except A19)
by refresh collisions require a corresponding number of additional CE# LOW cycles.
DQ[15:0]
CLK
LB#/UB#
(Note 2)
A[22:0]
ADV#
Bus Configuration Register
WAIT
WE#
OE#
CE#
CRE
A19
Figure 32. Configuration Register WRITE, Synchronous Mode Followed by READ0
Latch Control Register Value
The BCR defines how the CellularRAM device interacts with the system memory
bus. Page mode operation is enabled by a bit contained in the RCR.
below describes the control bits in the BCR. At power up, the BCR is set to 9D4Fh.
High-Z
t CSP
OPCODE
t SP
t SP
t SP
t SP
t CEW
A d v a n c e
t HD
t HD
t HD
t HD
Latch Control Register Address
I n f o r m a t i o n
CellularRAM Type 2
(Note 3)
t CBPH
High-Z
ADDRESS
ADDRESS
Table 18
Legend:
Don't care
VALID
DATA
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