S71GS128NB0 SPANSION [SPANSION], S71GS128NB0 Datasheet - Page 104

• Manufacturer Part Number: S71GS128NB0
• Description: 128N based MCPs
• Manufacturer: SPANSION [SPANSION]

Note: Functional block diagrams illustrate simplified device operation. See truth table, ball descriptions, and timing di-
agrams for detailed information.
104
128M: A[22:0]
64M: A[21:0]
32M: A[20:0]
ADV#
that part of the DRAM array that contains essential data. Temperature compen-
sated refresh (TCR) adjusts the refresh rate to match the device temperature—
the refresh rate decreases at lower temperatures to minimize current consump-
tion during standby. Deep power-down (DPD) enables the system to halt the
refresh operation altogether when no vital information is stored in the device. The
system-configurable refresh mechanisms are accessed through the RCR.
WAIT
WE#
OE#
UB#
CLK
CRE
CE#
LB#
Control
Logic
Figure 21. Functional Block Diagram
Refresh Configuration
Bus Configuration
Address Decode
Register (RCR)
Register (BCR)
A d v a n c e
Logic
CellularRAM Type 2
I n f o r m a t i o n
MEMORY
ARRAY
DRAM
Output
Buffers
Input/
MUX
and
cellRAM_00_A0 October 4, 2004
DQ[7:0]
DQ[15:8]