S71GS128NB0 SPANSION [SPANSION], S71GS128NB0 Datasheet - Page 163

• Manufacturer Part Number: S71GS128NB0
• Description: 128N based MCPs
• Manufacturer: SPANSION [SPANSION]

Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. If CE# goes
October 4, 2004 cellRAM_00_A0
DQ[15:0]
LB#/UB#
HIGH, it must remain HIGH for at least 5ns (t
Extended Timings Impact CellularRAM™ Operation”
A[22:0]
ADV#
WAIT
WE#
OE#
CE#
CLK
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V OH
V OL
V IH
V IL
Figure 57. Burst READ Followed by Asynchronous WRITE (WE#-Controlled)
High-Z
READ Burst Identified
t CEW
(WE# = HIGH)
Address
t CSP
t SP
t SP
t SP
Valid
t SP t HD
A d v a n c e
t HD
t HD
High-Z
t HD
t OLZ
t ACLK
I n f o r m a t i o n
t BOE
CBPH
t KHTL
CellularRAM Type 2
t CLK
) to schedule the appropriate internal refresh operation. See
t HD
Output
Valid
for restrictions on the maximum CE# LOW time (t
t KOH
t OHZ
t HZ
(Note 2)
t CBPH
High-Z
t CEW
Legend:
t AS
t BW
t CEM
Address
t AW
t CW
Valid
t WC
t WP
Don't Care
t DW
Input
Valid
t HZ
CEM
t WPH
Undefined
t DH
t WR
).
“How
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