S71GS128NB0 SPANSION [SPANSION], S71GS128NB0 Datasheet - Page 118

• Manufacturer Part Number: S71GS128NB0
• Description: 128N based MCPs
• Manufacturer: SPANSION [SPANSION]

118
Note: Burst wrap and length apply to READ operations only.
All must be set to "0"
BCR[19]
0
1
Reserved
22–20
Register Select
A[22:20]
Select RCR
Select BCR
Register
BCR[15]
Select
The BCR is accessed using CRE and A[19] HIGH.
0
1
Must be set to "0"
19
A19
BCR[13]
Reserved
0
0
0
0
1
1
1
1
Operating Mode
18–16
Synchronous burst access mode
Asynchronous access mode (default)
A[18:16]
BCR[12] BCR[11] Latency Counter
0
0
1
1
0
0
1
1
Operating
Mode
Table 18. Bus Configuration Register Definition
15
Must be set to "0"
A15
0
1
0
1
0
1
0
1
BCR[10]
Latency
0
1
Initial
14
A14
Code 0–Reserved
Code 1–Reserved
Code 2
Code 3 (Default)
Code 4
Code 5
Code 6
Code 7–Reserved
WAIT Polarity
Active LOW
Active HIGH (default)
13
Latency
Counter
A13
A d v a n c e
12
A12
CellularRAM Type 2
11
Polarity
A11
WAIT
Must be set to "0"
10
A10
Reserved
BCR[8]
9
0
1
A9
I n f o r m a t i o n
Configuration
BCR[2]
WAIT
(WC)
0
0
0
1
Must be set to "0"
WAIT Configuration
8
Asserted during delay
Asserted one data cycle before delay (default)
BCR[3]
0
1
Others
BCR[1] BCR[0] Burst Length (Note)
A8
0
1
1
1
BCR[5]
Reserved
0
0
1
1
Setting is ignored
Burst Wrap (Note)
1
0
1
1
7
Burst wraps within the burst length
Burst no wrap (default)
BCR[4]
A7
0
1
0
1
Reserved
4 words
8 words
16 words
Continuous burst (default)
Reserved
Output Impedance
6
1/2 Drive
1/4 Drive
Reserved
Full Drive (default)
A6
Impedance
Output
5
A5
cellRAM_00_A0 October 4, 2004
4
Burst
Wrap
(BW)
(Note)
A4
3
A3
Burst
Length
(BL)
(Note)
2
A2
1
A1 A0
0