S71GS128NB0 SPANSION [SPANSION], S71GS128NB0 Datasheet - Page 107

• Manufacturer Part Number: S71GS128NB0
• Description: 128N based MCPs
• Manufacturer: SPANSION [SPANSION]

Notes:
1. CLK may be HIGH or LOW, but must be static during asynchronous read, synchronous write, burst suspend, and
2. The WAIT polarity is configured through the bus configuration register (BCR[10]).
3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0]
4. The device will consume active power in this mode whenever addresses are changed.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any
6. V
7. DPD is maintained until RCR is reconfigured.
8. Burst mode operation is initialized through the bus configuration register (BCR[15]).
Functional Description
October 4, 2004 cellRAM_00_A0
Initial Burst Read
Initial Burst Write
Burst Continue
Burst Suspend
No Operation
Configuration
Async Write
DPD modes; and to achieve standby power during standby and active modes.
are affected. When only UB# is in the select mode, DQ[15:8] are affected.
external influence.
Async Read
IN
Standby
Register
MODE
DPD
= V
Power-Up Initialization
CC
Q or 0V; all device balls must be static (unswitched) to achieve standby current.
The CellularRAM bus interface supports both asynchronous and burst mode
transfers. Page mode accesses are also included as a bandwidth-enhancing ex-
tension to the asynchronous read protocol.
CellularRAM products include an on-chip voltage sensor used to launch the
power-up initialization process. Initialization will configure the BCR and the RCR
with their default settings (see
applied simultaneously. When they reach a stable level at or above 1.7V, the de-
vice will require 150µs to complete its self-initialization process. During the
initialization period, CE# should remain HIGH. When initialization is complete, the
device is ready for normal operation.
Power-Down
Standby
POWER
Active
Active
Active
Active
Active
Active
Active
Deep
Idle
A d v a n c e
(Note
CLK
X
X
X
X
X
X
Table 17. Bus Operations—Burst Mode
1) ADV#
X
X
H
X
X
L
L
L
L
L
I n f o r m a t i o n
CellularRAM Type 2
Table 18
CE#
H
H
L
L
L
L
L
L
L
L
OE#
X
X
X
X
H
X
H
H
X
L
and
Table
WE#
H
X
X
H
X
X
X
L
L
L
22). V
CRE
H
X
L
L
L
L
L
L
L
L
CC
LB#/
UB#
and V
X
X
X
X
X
X
X
L
L
L
CC
(Note
High-Z
High-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
WAIT
Q must be
2)
Data-In or
Data-Out
Data-Out
Data-Out
DQ[15:0]
(Note
Data-In
Data-In
High-Z
High-Z
High-Z
High-Z
X
3)
NOTES
5,
4,
4,
4,
4,
4,
4
4
8
7
6
6
8
8
8
8
107