ZL50400GDC ZARLINK [Zarlink Semiconductor Inc], ZL50400GDC Datasheet - Page 99

• Manufacturer Part Number: ZL50400GDC
• Description: Lightly Managed/Unmanaged 9-Port 10/100 M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

12.3.9.3
I²C Address h06A+n, CPU Address 840+n (n = port number)
Accessed by CPU and I²C (R/W)
Expressed in multiples of 16 granules. (Default 0x6)
12.3.9.4
I²C Address h073, CPU Address 848
Accessed by CPU and I²C (R/W)
Expressed in multiples of 16 granules. (Default 0x6)
12.3.9.5
I²C Address h072, CPU Address 849
Accessed by CPU and I²C (R/W)
Expressed in multiples of 16 granules. (Default 0x24)
12.3.9.6
I²C Address h0C2+n, CPU Address 860+n (n = port number)
Accessed by CPU and I²C (R/W)
Expressed in multiples of 16 granules. More than this number used on a source port will trigger either random drop
or flow control (Default 0x3)
12.3.9.7
I²C Address h0CB, CPU Address 868
Accessed by CPU and I²C (R/W)
Expressed in multiples of 16 granules. More than this number used on a source port will trigger either random drop
or flow control (Default 0x3)
12.3.9.8
I²C Address h0CA, CPU Address 869
Accessed by CPU and I²C (R/W)
Expressed in multiples of 16 granules. More than this number used on a source port will trigger either random drop
or flow control (Default 0x12)
12.3.9.9
Accessed by CPU and I²C (R/W)
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QOSC00 – BYTE_L1 (I²C Address h078, CPU Address 880)
QOSC01 – BYTE_L2 (I²C Address h079, CPU Address 881)
Bits [7:4]:
PR100_n – Port 0~7 Reservation
PR100_CPU – Port CPU Reservation
PRM – Port MMAC Reservation
PTH100_n – Port 0~7 Threshold
PTH100_CPU – Port CPU Threshold
PTHG – Port MMAC Threshold
QOSC00, QOSC01 - Classes Byte Limit port 0
Broadcast Rate Control. Number of broadcast packets allowed within the time defined
in bits 6 to 4 of the Flooding Control Register (FCRn). (Default 0)
Zarlink Semiconductor Inc.
ZL50400
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Data Sheet