ZL50400GDC ZARLINK [Zarlink Semiconductor Inc], ZL50400GDC Datasheet - Page 60

• Manufacturer Part Number: ZL50400GDC
• Description: Lightly Managed/Unmanaged 9-Port 10/100 M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

12.2
12.2.1
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12.2.2
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12.2.3
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12.2.4
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F. System Control
GCR
DCR
DCR1
DPST
DTST
DA
Address for indirectly accessed register addresses (16 bits)
Address = 0 (write only)
Data of indirectly accessed registers (8 bits)
Address = 2 (read/write)
CPU transmit/receive switch frames (16 bits)
Address = 3 (read/write)
Format:
CPU interface commands and status (8 bits)
Address = 4 (read/write)
When the CPU writes to this register
Directly Accessed Registers
Register
INDEX_REG0
DATA_FRAME_REG
CONTROL_FRAME_REG
COMMAND&STATUS Register
8-byte of Frame status (Frame size, Source port #, VLAN tag)
Frame Data (size should be in multiple of 8-byte)
Global Control Register
Device Control Register
Device Control Register 1
Device Port Status Register
Data read back register
DA Register
Table 12 - Register Description (continued)
Description
Zarlink Semiconductor Inc.
ZL50400
60
CPU Addr
(Hex)
FFF
F00
F01
F02
F03
F04
R/W
R/W
R/W
RO
RO
RO
RO
(Hex)
Addr
NA
NA
NA
NA
NA
NA
I²C
Default
0DA
000
000
NA
NA
NA
Data Sheet
Notes