ZL50400GDC ZARLINK [Zarlink Semiconductor Inc], ZL50400GDC Datasheet - Page 91

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ZL50400GDC

Manufacturer Part Number
ZL50400GDC
Description
Lightly Managed/Unmanaged 9-Port 10/100 M Ethernet Switch
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
12.3.6.35
I²C Address h0AE, CPU Address: 5A0
Accessed by CPU and I²C (R/W)
12.3.6.36
I²C Address h0AF, CPU Address: 5A1
Accessed by CPU and I²C (R/W)
12.3.6.37
I²C Address h0B0, CPU Address: 5A2
Accessed by CPU and I²C (R/W)
12.3.6.38
I²C Address h0B1, CPU Address: 5A3
Accessed by CPU and I²C (R/W)
12.3.6.39
I²C Address h0B2, CPU Address: 5A4
Accessed by CPU and I²C (R/W)
RLOW and RHIGH form a range for logical ports to be classified with priority specified in RPRIORITY.
Bits [7:0]:
Bits [7:0]:
Bits [7:0]:
Bits [7:0]:
Bit [0]:
Bits [3:1]
Bits [5:4]
Bits [7:6]
RLOWL – User Define Range Low Bit 7:0
RLOWH – User Define Range Low Bit 15:8
RHIGHL – User Define Range High Bit 7:0
RHIGHH – User Define Range High Bit 15:8
RPRIORITY – User Define Range Priority
Lower 8 bit of the User Define Logical Port Low Range
Upper 8 bit of the User Define Logical Port Low Range
Lower 8 bit of the User Define Logical Port High Range
Upper 8 bit of the User Define Logical Port High Range
Drop Priority (inclusive only)
Transmit Priority (inclusive only)
Reserved
00 - No Filtering
01 - Exclusive Filtering (x<=RLOW or x>=RHIGH)
10 - Inclusive Filtering (RLOW<x<RHIGH)
11 - Invalid
Zarlink Semiconductor Inc.
ZL50400
91
Data Sheet

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