ZL50400GDC ZARLINK [Zarlink Semiconductor Inc], ZL50400GDC Datasheet - Page 111

• Manufacturer Part Number: ZL50400GDC
• Description: Lightly Managed/Unmanaged 9-Port 10/100 M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

12.3.11.3
CPU Address: hF02
Accessed by CPU (RO)
12.3.11.4
CPU Address:hF03
Accessed by CPU (R/W)
12.3.11.5
CPU Address: hF04
Accessed by CPU (RO)
This register provides various internal information as selected in DPST bit [4:0]. Refer to the PHY Port Control
Application Note, ZLAN-37.
Bits [6:0]
Bit [7]
Bits [4:0]:
Bits [7:5]:
Bit [0]
Bit [1]
Bit [2]
Bit [3]
DPST – Device Port Status Register
DTST – Data read back register
DCR1 - Device Status Register 1
Reserved
Chip initialization completed
Read back index register. This is used for selecting what to read back from
DTST. (Default 00)
Reserved
Flow control enable
1: Flow control
0: No flow control
Full duplex port
1: Full duplex
0: Half duplex
Fast Ethernet port
1: FE Port
Link is down
1: Link down
0: Link up
-
-
-
-
-
-
-
-
-
-
5’b00000 - Port 0 Operating mode and Negotiation status
5’b00001 - Port 1 Operating mode and Negotiation status
5’b00010 - Port 2 Operating mode and Negotiation status
5’b00011 - Port 3 Operating mode and Negotiation status
5’b00100 - Port 4 Operating mode and Negotiation status
5’b00101 - Port 5 Operating mode and Negotiation status
5’b00110 - Port 6 Operating mode and Negotiation status
5’b00111 - Port 7 Operating mode and Negotiation status
5’b01000 - Port CPU Operating mode and Negotiation status
5’b01001 - Port MMAC Operating mode and Negotiation status
Zarlink Semiconductor Inc.
ZL50400
111
Data Sheet