ZL50400GDC ZARLINK [Zarlink Semiconductor Inc], ZL50400GDC Datasheet - Page 103

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ZL50400GDC

Manufacturer Part Number
ZL50400GDC
Description
Lightly Managed/Unmanaged 9-Port 10/100 M Ethernet Switch
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
12.3.10.7
CPU Address EA0+n
Accessed by CPU (RO)
12.3.10.8
CPU Address EA8 – EA9
Accessed by CPU (RO)
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
Bit [8]:
Bit [9]:
Bit [10]:
Bit [11]:
Bit [12]:
Bit [13]:
Bits [15:14]:
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
PRTQOSST0-PRTQOSST7
PRTQOSST8A, PRTQOSST8B (CPU port)
Source port reservation low
No source port buffer left
Unicast congestion detected on best effort queue
Reserved
High priority queue reach L1 WRED level
High priority queue reach L2 WRED level
Low priority MC queue full
High priority MC queue full
Source port reservation low
No source port buffer left
Unicast congestion detected on best effort queue
Reserved
priority queue 1 reach L1 WRED level
priority queue 1 reach L2 WRED level
priority queue 2 reach L1 WRED level
priority queue 2 reach L2 WRED level
priority queue 3 reach L1 WRED level
priority queue 3 reach L2 WRED level
priority 0 MC queue full
priority 1 MC queue full
priority 2 MC queue full
Priority 3 MC queue full
Reserved
15
PQSTB
Zarlink Semiconductor Inc.
ZL50400
103
PQSTA
0
Data Sheet

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