ZL50400GDC ZARLINK [Zarlink Semiconductor Inc], ZL50400GDC Datasheet - Page 75

• Manufacturer Part Number: ZL50400GDC
• Description: Lightly Managed/Unmanaged 9-Port 10/100 M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

12.3.4.9
INTP_MASK1 CPU Address:h311 (Ports 2,3)
INTP_MASK2 CPU Address:h312 (Ports 4,5)
INTP_MASK3 CPU Address:h313 (Ports 6,7)
INTP_MASK4 CPU Address:h314 (Port CPU,MMAC)
12.3.4.10
CPU Address:h323
Accessed by CPU (RW)
Select which receive queue is being used by the CPU port.
Note: Strict priority applies between different selected queues (UQ3>UQ2>UQ1>UQ0>MQ3>MQ2>MQ1>MQ0).
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]
-
0: Unmask the interrupt (Default)
INTP_MASKn – Interrupt Mask for MAC Ports 2~9 Registers
Port 0 statistic counter wrap around interrupt mask. An Interrupt is generated when a statistic
counter wraps around. Refer to hardware statistic counter for interrupt sources
Port 0 link change mask
Port 0 module detect mask
Reserved
Port 1 statistic counter wrap around interrupt mask. An interrupt is generated when a statistic
counter wraps around. Refer to hardware statistic counter for interrupt sources.
Port 1 link change mask
Port 1 module detect mask
Reserved
RQS – Receive Queue Select
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
Select Queue 0
0: Not selected (Default)
1: Selected
Select Queue 1
Select Queue 2
Select Queue 3
Select Multicast Queue 0
Select Multicast Queue 1
Select Multicast Queue 2
Select Multicast Queue 3
Zarlink Semiconductor Inc.
ZL50400
75
Data Sheet