ZL50400GDC ZARLINK [Zarlink Semiconductor Inc], ZL50400GDC Datasheet - Page 74

• Manufacturer Part Number: ZL50400GDC
• Description: Lightly Managed/Unmanaged 9-Port 10/100 M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

12.3.4.4
CPU Address:h303
Accessed by CPU (R/W)
12.3.4.5
CPU Address:h304
Accessed by CPU (R/W)
12.3.4.6
CPU Address:h305
Accessed by CPU (R/W)
12.3.4.7
CPU Address:h306
Accessed by CPU (R/W)
The CPU can dynamically mask the interrupt when it is busy and doesn’t want to be interrupted. (Default 0x00)
12.3.4.8
CPU Address:h310
Accessed by CPU (R/W)
The CPU can dynamically mask the interrupt when it is busy and doesn’t want to be interrupted (Default 0x00)
-
-
-
Bit [0]:
Bit [1]:
Bit [2]:
Bits [6:3]:
Bit [7]:
1: Mask the interrupt
0: Unmask the interrupt (Enable interrupt) (Default)
1: Mask the interrupt
Bits [7:0]:
Bits [7:0]:
Bits [7:0]:
MAC3 – CPU MAC address byte 3
MAC4 – CPU MAC address byte 4
MAC5 – CPU MAC address byte 5
INT_MASK0 – Interrupt Mask
INTP_MASK0 – Interrupt Mask for MAC Port 0,1
CPU frame interrupt. CPU frame buffer has data for CPU to read
Control Command 1 interrupt. Control Command Frame buffer1 has data for CPU to read
Control Command 2 interrupt. Control command Frame buffer2 has data for CPU to read
Reserved
Device Timeout Detected interrupt
Byte 4 (bits [39:32]) of the CPU MAC address (Default 0)
Note: Bits [42:40] are set on a per port basis using MAC01, MAC23, MAC45,
MAC67 registers. For port 9, this register is ignored and MAC9 is used for bits
[47:40].
Byte 5 (bits [47:40]) of the CPU MAC address (Default 0)
Byte 3 (bits [31:24]) of the CPU MAC address (Default 0)
Zarlink Semiconductor Inc.
ZL50400
74
Data Sheet