ZL50400GDC ZARLINK [Zarlink Semiconductor Inc], ZL50400GDC Datasheet - Page 95

• Manufacturer Part Number: ZL50400GDC
• Description: Lightly Managed/Unmanaged 9-Port 10/100 M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

12.3.7.10
CPU Address:h609
Accessed by CPU (R/W)
12.3.7.11
CPU Address:h60A
Accessed by CPU (R/W)
12.3.7.12
I²C Address 0FF, CPU Address:h60B
Accessed by CPU and I²C (R/W)
This register is used in unmanaged mode only. Before requesting that the ZL50400 updates the EEPROM device,
the correct checksum needs to be calculated and written into this checksum register.
The checksum formula is:
When the ZL50400 boots from the EEPROM the checksum is calculated and the value must be zero. If the
checksum is not zeroed the ZL50400 does not start and pin CHECKSUM_OK is set to zero.
Bits [5:0]:
Bits [7:6]:
Bit [0]:
Bit [1]:
Bits [7:2]:
Bits [7:0]:
DEVICE Mode
USD – One Micro Second Divider
CHECKSUM - EEPROM Checksum
Divider to get one micro second from M_CLK (only used when not in standard RMII mode)
In a MII or GPSI system, a 50 MHz M_CLK may not be available. The system designer can
decide to use another frequency on the M_CLK signal. To compensate for this, this register
is required to be programmed.
For example. If 20 MHz is used on M_CLK, to compensate for the difference, this register is
programmed with 20 to provide 1usec for internal reference.
Reserved
FF
Σ
i = 0
I²C register = 0
Reserved
CPU Interrupt Polarity
0: Negative Polarity
1: Positive Polarity (Default)
Reserved
Checksum content (Default 0)
Zarlink Semiconductor Inc.
ZL50400
95
Data Sheet