ZL50400GDC ZARLINK [Zarlink Semiconductor Inc], ZL50400GDC Datasheet - Page 79

• Manufacturer Part Number: ZL50400GDC
• Description: Lightly Managed/Unmanaged 9-Port 10/100 M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

12.3.4.21
CPU Address:h33f
Accessed by CPU, (R/W)
CPU receive queue status
12.3.5
12.3.5.1
I²C Address h049; CPU Address:h400
Accessed by CPU and I²C (R/W)
Used in conjuction with AGETIME_HIGH. The ZL50400 removes the MAC address from the data base and sends a
Delete MAC Address Control Command to the CPU.
12.3.5.2
I²C Address h04A; CPU Address h401
Accessed by CPU and I²C (R/W)
The default setting of AGETIME_LOW/HIGH provides 300 seconds aging time. Aging time is based on the
following equation:
{AGETIME_HIGH,AGETIME_LOW} X (# of MAC entries in the memory X 800 µsec). Number of MAC entries = 4 K.
12.3.5.3
CPU Address:h403
Accessed by CPU (R/W)
Note: ECR2[2] enable/disable learning for each port.
Bit [0]:
Bit [1]:
Bit [2]:
Bits [7:0]:
Bits [7:0]:
(Group 4 Address) Search Engine Group
Bit [0]:
Bit [1]:
AGETIME_LOW – MAC address aging time Low
AGETIME_HIGH –MAC address aging time High
SE_OPMODE – Search Engine Operation Mode
CPUGRNCTR – CPU Granule Control
Allocate granule to the CPU if set to one. Otherwise, do not allocate any resource.
Read allocated granule (at rising edge only)
Release info valid (will be processed at rising edge only)
Low byte of the MAC address aging timer (Default 0x5C)
High byte of the MAC address aging timer (Default 0x00)
Reserved. Must be 0.
Protocol filtering mode
0 – Inclusive (Default)
1 – Exclusive
Zarlink Semiconductor Inc.
ZL50400
79
Data Sheet