ZL50400GDC ZARLINK [Zarlink Semiconductor Inc], ZL50400GDC Datasheet - Page 110

• Manufacturer Part Number: ZL50400GDC
• Description: Lightly Managed/Unmanaged 9-Port 10/100 M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

12.3.11
12.3.11.1
CPU Address: hF00
Accessed by CPU (R/W)
12.3.11.2
CPU Address: hF01
Accessed by CPU (RO)
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bits [7:5]:
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bits [5:4]:
Bits [7:6]:
(Group F Address) CPU Access Group
DCR - Device Status and Signature Register
GCR - Global Control Register
Store configuration (Default = 0)
Write ‘1’ followed by ‘0’ to store configuration into external EEPROM
Store configuration and reset (Default = 0)
Write ‘1’ to store configuration into external EEPROM and reset chip
Start BIST (Default = 0)
Write ‘1’ followed by ‘0’ to start the device’s built-in self-test. The result is
found in the DCR register.
Soft Reset (Default = 0)
Write ‘1’ to reset chip
Initialization Completed (Default = 0)
This bit is reserved in unmanaged mode.
In managed mode, the CPU writes this bit with ‘1’ to indicate initialization is
completed and ready to forward packets. The ‘0' to '1' transition will toggle
TSTOUT[2] from low to high.
Reserved
1: Busy writing configuration to I²C
0: Not busy (not writing configuration to I²C)
1: Busy reading configuration from I²C
0: Not busy (not reading configuration from I²C)
1: BIST in progress
0: BIST not running
1: RAM Error
0: RAM OK
Device Signature
10: ZL50400 device
Revision
00: Initial Silicon
01: Second Silicon
Zarlink Semiconductor Inc.
ZL50400
110
Data Sheet