MC9S08GB32 Motorola, MC9S08GB32 Datasheet - Page 91

• Manufacturer Part Number: MC9S08GB32
• Description: Microcontrollers
• Manufacturer: Motorola

PTEDn — Port E Data Register Bit n (n = 0–7)
PTEPEn — Pullup Enable for Port E Bit n (n = 0–7)
PTESEn — Slew Rate Control Enable for Port E Bit n (n = 0–7)
Freescale Semiconductor
For port E pins that are inputs, reads return the logic level on the pin. For port E pins that are configured
as outputs, reads return the last value written to this register.
Writes are latched into all bits in this register. For port E pins that are configured as outputs, the logic
level is driven out the corresponding MCU pin.
Reset forces PTED to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
For port E pins that are inputs, these read/write control bits determine whether internal pullup devices
are enabled. For port E pins that are configured as outputs, these bits are ignored and the internal pullup
devices are disabled.
For port E pins that are outputs, these read/write control bits determine whether the slew rate controlled
outputs are enabled. For port E pins that are configured as inputs, these bits are ignored.
PTED
PTEPE
PTESE
PTEDD
1 = Internal pullup device enabled.
0 = Internal pullup device disabled.
1 = Slew rate control enabled.
0 = Slew rate control disabled.
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PTEPE7
PTESE7
PTEDD7
PTED7
Bit 7
0
0
0
0
PTEPE6
PTESE6
PTEDD6
MC9S08GB/GT Data Sheet, Rev. 2.3
PTED6
Figure 6-13. Port E Registers
6
0
0
0
0
PTEDD5
PTEPE5
PTESE5
PTED5
5
0
0
0
0
PTEDD4
PTEPE4
PTESE4
PTED4
4
0
0
0
0
PTEDD3
PTEPE3
PTESE3
PTED3
3
0
0
0
0
PTEDD2
PTEPE2
PTESE2
PTED2
Parallel I/O Registers and Control Bits
2
0
0
0
0
PTEDD1
PTEPE1
PTESE1
PTED1
1
0
0
0
0
PTEDD0
PTEPE0
PTESE0
PTED0
Bit 0
0
0
0
0
91