MC9S08GB32 Motorola, MC9S08GB32 Datasheet - Page 215

• Manufacturer Part Number: MC9S08GB32
• Description: Microcontrollers
• Manufacturer: Motorola

13.5.3
IICEN — IIC Enable
IICIE — IIC Interrupt Enable
MST — Master Mode Select
TX — Transmit Mode Select
TXAK — Transmit Acknowledge Enable
Freescale Semiconductor
The IICEN bit determines whether the IIC module is enabled.
The IICIE bit determines whether an IIC interrupt is requested.
The MST bit is changed from a 0 to a 1 when a START signal is generated on the bus and master mode
is selected. When this bit changes from a 1 to a 0 a STOP signal is generated and the mode of operation
changes from master to slave.
The TX bit selects the direction of master and slave transfers. In master mode this bit should be set
according to the type of transfer required. Therefore, for address cycles, this bit will always be high.
When addressed as a slave this bit should be set by software according to the SRW bit in the status
register.
This bit specifies the value driven onto the SDA during data acknowledge cycles for both master and
slave receivers.
1 = IIC is enabled.
0 = IIC is not enabled.
1 = IIC interrupt request enabled.
0 = IIC interrupt request not enabled.
1 = Master Mode.
0 = Slave Mode.
1 = Transmit.
0 = Receive.
1 = No acknowledge signal response is sent.
0 = An acknowledge signal will be sent out to the bus after receiving one data byte.
IIC Control Register (IIC1C)
Reset:
Read:
Write:
IICEN
Bit 7
0
Figure 13-7. IIC Control Register (IIC1C)
= Unimplemented or Reserved
MC9S08GB/GT Data Sheet, Rev. 2.3
IICIE
6
0
MST
5
0
TX
4
0
TXAK
3
0
RSTA
2
0
0
Inter-Integrated Circuit (IIC) Module
1
0
0
Bit 0
0
0
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