MC9S08GB32 Motorola, MC9S08GB32 Datasheet - Page 74

• Manufacturer Part Number: MC9S08GB32
• Description: Microcontrollers
• Manufacturer: Motorola

Chapter 5 Resets, Interrupts, and System Configuration
5.8.7
LVDF — Low-Voltage Detect Flag
LVDACK — Low-Voltage Detect Acknowledge
LVDIE — Low-Voltage Detect Interrupt Enable
74
1
2
See
t
1
Provided LVDE = 1, this read-only status bit indicates a low-voltage detect event.
This write-only bit is used to acknowledge low voltage detection errors (write 1 to clear LVDF). Reads
always return 0.
This read/write bit enables hardware interrupt requests for LVDF.
RTIS2:RTIS1:RTIS0
ext
This bit can be written only one time after reset. Additional writes are ignored.
is based on the external clock source, resonator, or crystal selected by the ICG configuration. See
1 = Request a hardware interrupt when LVDF = 1.
0 = Hardware interrupt disabled (use polling).
Table A-10
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
System Power Management Status and Control 1 Register (SPMSC1)
Figure 5-8. System Power Management Status and Control 1 Register (SPMSC1)
t
RTI
Reset:
Read:
Write:
in
Appendix A, “Electrical
LVDF
Bit 7
0
Disable periodic wakeup timer
Internal Clock Source
(t
Table 5-2. Real-Time Interrupt Period
RTI
= Unimplemented or Reserved
LVDACK
MC9S08GB/GT Data Sheet, Rev. 2.3
= 1 ms, Nominal)
6
0
0
128 ms
256 ms
512 ms
1.024 s
32 ms
64 ms
8 ms
Characteristics” for the tolerance on these values.
LVDIE
5
0
1
LVDRE
4
1
1
LVDSE
3
1
(1)
Disable periodic wakeup timer
External Clock Source
LVDE
2
1
(1)
Period = t
t
t
t
ext
t
t
t
ex
t
ext
ex
ex
ex
ext
x 32768
x 16384
x 1024
x 2048
x 4096
x 8192
x 256
Freescale Semiconductor
1
0
0
ext
Table A-9
Bit 0
2
0
0
for details.