MC9S08GB32 Motorola, MC9S08GB32 Datasheet - Page 166
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MC9S08GB32
Manufacturer Part Number
MC9S08GB32
Description
Microcontrollers
Manufacturer
Motorola
Datasheet
1.MC9S08GB32.pdf
(290 pages)
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Timer/PWM (TPM) Module
In input capture mode, reading either byte (TPMxCnVH or TPMxCnVL) latches the contents of both bytes
into a buffer where they remain latched until the other byte is read. This latching mechanism also resets
(becomes unlatched) when the TPMxCnSC register is written.
In output compare or PWM modes, writing to either byte (TPMxCnVH or TPMxCnVL) latches the value
into a buffer. When both bytes have been written, they are transferred as a coherent 16-bit value into the
timer channel value registers. This latching mechanism may be manually reset by writing to the
TPMxCnSC register.
This latching mechanism allows coherent 16-bit writes in either order, which is friendly to various
compiler implementations.
166
Reset:
Reset:
Figure 10-11. Timer x Channel Value Register High (TPMxCnVH)
Read:
Write:
Read:
Write:
Figure 10-12. Timer x Channel Value Register Low (TPMxCnVL)
Bit 15
Bit 7
Bit 7
Bit 7
0
0
MC9S08GB/GT Data Sheet, Rev. 2.3
14
6
0
6
6
0
13
5
0
5
5
0
12
4
0
4
4
0
11
3
0
3
3
0
10
2
0
2
2
0
Freescale Semiconductor
1
9
0
1
1
0
Bit 0
Bit 8
Bit 0
Bit 0
0
0
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