MC9S08GB32 Motorola, MC9S08GB32 Datasheet - Page 88

• Manufacturer Part Number: MC9S08GB32
• Description: Microcontrollers
• Manufacturer: Motorola

Chapter 6 Parallel Input/Output
PTCDn — Port C Data Register Bit n (n = 0–7)
PTCPEn — Pullup Enable for Port C Bit n (n = 0–7)
PTCSEn — Slew Rate Control Enable for Port C Bit n (n = 0–7)
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For port C pins that are inputs, reads return the logic level on the pin. For port C pins that are configured
as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port C pins that are configured as outputs, the logic
level is driven out the corresponding MCU pin.
Reset forces PTCD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
For port C pins that are inputs, these read/write control bits determine whether internal pullup devices
are enabled. For port C pins that are configured as outputs, these bits are ignored and the internal pullup
devices are disabled.
For port C pins that are outputs, these read/write control bits determine whether the slew rate controlled
outputs are enabled. For port B pins that are configured as inputs, these bits are ignored.
PTCD
PTCPE
PTCSE
PTCDD
1 = Internal pullup device enabled.
0 = Internal pullup device disabled.
1 = Slew rate control enabled.
0 = Slew rate control disabled.
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PTCDD7 PTCDD6 PTCDD5 PTCDD4 PTCDD3 PTCDD2 PTCDD1 PTCDD0
PTCPE7
PTCSE7
PTCD7
Bit 7
0
0
0
0
PTCPE6
PTCSE6
MC9S08GB/GT Data Sheet, Rev. 2.3
PTCD6
Figure 6-11. Port C Registers
6
0
0
0
0
PTCPE5
PTCSE5
PTCD5
5
0
0
0
0
PTCPE4
PTCSE4
PTCD4
4
0
0
0
0
PTCPE3
PTCSE3
PTCD3
3
0
0
0
0
PTCPE2
PTCSE2
PTCD2
2
0
0
0
0
PTCPE1
PTCSE1
PTCD1
Freescale Semiconductor
1
0
0
0
0
PTCPE0
PTCSE0
PTCD0
Bit 0
0
0
0
0