HYB18T512160A Infineon Technologies AG, HYB18T512160A Datasheet - Page 9

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HYB18T512160A

Manufacturer Part Number
HYB18T512160A
Description
512-Mbit Double-Data-Rate-Two SDRAM
Manufacturer
Infineon Technologies AG
Datasheet

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1.4
The pin configuration of a DDR2 SDRAM is listed by function in
Type columns are explained in
depicted in
Table 3
Ball#/Pin#
Clock Signals 4/ 8 organizations
E8
F8
F2
Clock Signals 16 organization
J8
K8
K2
Control Signals 4/ 8 organizations
F7
G7
F3
G8
Control Signals 16 organization
K7
L7
K3
L8
Address Signals 4/ 8 organizations
G2
G3
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
Data Sheet
Figure 1
Pin Configuration
Pin Configuration of DDR SDRAM
Name
CK
CK
CKE
CK
CK
CKE
RAS
CAS
WE
CS
RAS
CAS
WE
CS
BA0
BA1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
A13
for 4,
Pin
Type
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Figure 2
Table 4
SSTL
SSTL
SSTL
SSTL
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
for 8 and
and
Table 5
Function
Clock Signal
Complementary Clock Signal
Clock Enable Rank
Clock Signal
Complementary Clock Signal
Clock Enable Rank
Row Address Strobe
Column Address Strobe
Write Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Chip Select
Bank Address Bus 1:0
Address Signal 12:0
Address Signal 13
Figure 3
respectively. The pin numbering for the FBGA package is
9
for 16
512-Mbit Double-Data-Rate-Two SDRAM
Table
HYB18T512[400/800/160]A[C/F]–[3.7/5]
3. The abbreviations used in the Pin#/Buffer
09112003-SDM9-IQ3P
Rev. 1.13, 2004-05
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