HYB18T512160A Infineon Technologies AG, HYB18T512160A Datasheet - Page 32

• Manufacturer Part Number: HYB18T512160A
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: Infineon Technologies AG

ODT Truth Tables
The ODT Truth Table shows which of the input pins are
terminated depending on the state of address bit A10
and A11 in the EMRS(1) for all three device
Table 11
Input Pin
DQ[3:0]
DQS
DQS
DM
DQ[7:0]
DQS
DQS
RDQS
RDQS
DM
DQ[15:0]
LDQS
LDQS
UDQS
UDQS
LDM
UDM
Note: X = don’t care; 0 = bit set to low; 1 = bit set to high
ODT timing modes
Depending on the operating mode synchronous or
asynchronous ODT timings apply. Synchronous
timings (
when the on-die DLL is enabled.
These modes are:
•
•
•
Data Sheet
4 components
8 components
16 components
Active Mode
Standby Mode
Fast Exit Active Power Down Mode (with MRS bit
A12 is set to “0”)
t
AOND
ODT Truth Table
,
t
AOFD
,
t
AON
EMRS(1)
Address Bit A10
X
X
0
X
X
X
0
X
0
X
X
X
0
X
0
X
X
and
t
AOF
) apply for all modes,
32
organisations ( 4, 8 and 16). To activate termination
of any of these pins, the ODT function has to be
enabled in the EMRS(1) by address bits A6 and A2.
Asynchronous ODT timings (
the on-die DLL is disabled.
These modes are:
•
•
512-Mbit Double-Data-Rate-Two SDRAM
Slow Exit Active Power Down Mode (with MRS bit
A12 is set to “1”)
Precharge Power Down Mode
EMRS(1)
Address Bit A11
X
X
X
X
X
X
X
1
1
0
X
X
X
X
X
X
X
HYB18T512[400/800/160]A[C/F]–[3.7/5]
t
AOFPD
Functional Description
09112003-SDM9-IQ3P
,
Rev. 1.13, 2004-05
t
AONPD
) apply when