HYB18T512160A Infineon Technologies AG, HYB18T512160A Datasheet - Page 52

• Manufacturer Part Number: HYB18T512160A
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: Infineon Technologies AG

2.8
Before a new row in an active bank can be opened, the
active bank must be precharged using either the Pre-
charge Command or the Auto-Precharge function.
When a Read or a Write Command is given to the
DDR2 SDRAM, the CAS timing accepts one extra
address, column address A10, to allow the active bank
to automatically begin precharge at the earliest
possible moment during the burst read or write cycle. If
A10 is low when the Read or Write Command is issued,
then the Auto-Precharge function is enabled.
During Auto-Precharge, a Read Command will execute
as normal with the exception that the active bank will
begin to precharge internally on the rising edge which
is CAS Latency (CL) clock cycles before the end of the
read burst.
2.8.1
If A10 is high when a Read Command is issued, the
Read with Auto-Precharge function is engaged. The
DDR2 SDRAM starts an Auto-Precharge operation on
the rising edge which is (AL + BL/2) cycles later from
the Read with AP command if
satisfied. If
point of Auto-Precharge operation will be delayed until
t
the start point of Auto-Precharge operation will be
delayed until
In case the internal precharge is pushed out by
starts at the point where the internal precharge
happens (not at the next rising clock edge after this
event). So for BL = 4 the minimum time from Read with
Auto-Precharge to the next Activate command
Data Sheet
RAS(min)
is satisfied. If
t
RAS(min)
Auto-Precharge Operation
Read with Auto-Precharge
t
RTPmin
is not satisfied at the edge, the start
is satisfied.
t
RTPmin
is not satisfied at the edge,
t
RAS(min)
and
t
RTP
t
RTP
are
,
t
RP
52
Auto-Precharge is also implemented for Write
Commands.The precharge operation engaged by the
Auto-Precharge command will not begin until the last
data of the write burst sequence is properly stored in
the memory array. This feature allows the precharge
operation to be partially or completely hidden during
burst read cycles (dependent upon CAS Latency) thus
improving system performance for random data
access.
The RAS lockout circuit internally delays the precharge
operation until the array restore operation has been
completed so that the Auto-Precharge command may
be issued with any read or write command.
becomes AL +
with Auto-Precharge to the next Activate command is
AL + 2 +
rounded up to the next integer value. In any event
internal precharge does not start earlier than two clocks
after the last 4-bit prefetch.
A new bank active (command) may be issued to the
same bank if the following two conditions are satisfied
simultaneously:
1. The RAS precharge time (
2. The RAS cycle time (
512-Mbit Double-Data-Rate-Two SDRAM
from the clock at which the Auto-Precharge begins.
activation has been satisfied.
HYB18T512[400/800/160]A[C/F]–[3.7/5]
t
RTP
+
t
RTP
t
RP
. Note that (
+
t
RP
. For BL = 8 the time from Read
t
RC
) from the previous bank
t
Functional Description
t
RP
RTP
09112003-SDM9-IQ3P
) has been satisfied
+
Rev. 1.13, 2004-05
t
RP
) has to be