HYB18T512160A Infineon Technologies AG, HYB18T512160A Datasheet - Page 77

• Manufacturer Part Number: HYB18T512160A
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: Infineon Technologies AG

6
Table 36
Parameter
Operating Current 0
One bank Active - Precharge;
high between valid commands. Address and control inputs are SWITCHING, Databus inputs
are SWITCHING
Operating Current 1
One bank Active - Read - Precharge;
t
Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Power-Down Current
All banks idle; CKE is LOW;
bus inputs are FLOATING
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
SWITCHING, Data bus inputs are SWITCHING.
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
STABLE, Data bus inputs are FLOATING.
Active Power-Down Current
All banks open;
bus inputs are FLOATING. MRS A12 bit is set to “0” (Fast Power-down Exit);
Active Power-Down Current
All banks open;
bus inputs are FLOATING. MRS A12 bit is set to “1” (Slow Power-down Exit);
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
t
are SWITCHING; Data Bus inputs are SWITCHING;
Operating Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
t
are SWITCHING; Data Bus inputs are SWITCHING;
Operating Current
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL
t
are SWITCHING; Data Bus inputs are SWITCHING;
Burst Refresh Current
t
between valid commands, Other control and address inputs are SWITCHING, Data bus
inputs are SWITCHING.
Distributed Refresh Current
t
between valid commands, Other control and address inputs are SWITCHING, Data bus
inputs are SWITCHING.
Data Sheet
RASmin.
RAS
RAS
RAS
CK
CK
=
=
=
=
=
t
t
t
t
t
CKmin
CKmin.
,
RASmax.
RASmax.
RASmax.
t
RCD
., Refresh command every
, Refresh command every
=
I
I
,
,
,
DD
DD
t
t
t
t
RP
RP
RP
RCDmin.
t
t
CK
CK
Measurement Conditions
.
=
=
=
Specifications and Conditions
=
=
t
t
t
RPmin.
RPmin.
RPmin.
t
t
,AL = 0, CL = CL
CKmin.
CKmin.
; CKE is HIGH, CS is high between valid commands. Address inputs
; CKE is HIGH, CS is high between valid commands. Address inputs
; CKE is HIGH, CS is high between valid commands. Address inputs
.
, CKE is LOW; Other control and address inputs are STABLE, Data
, CKE is LOW; Other control and address inputs are STABLE, Data
t
CK
t
CK
=
=
t
CKmin
t
CKmin.
min
t
I
t
RFC
OUT
RFC
;
Other control and address inputs are STABLE, Data
.; CKE is HIGH, CS is high between valid commands.
,
t
t
=
=
= 0 mA, BL = 4,
t
CK
CK
RC
t
t
REFI
RFCmin.
=
=
=
t
t
CKmin.
CKmin.
t
RCmin
interval, CKE is LOW and CS is HIGH
interval, CKE is HIGH, CS is HIGH
I
I
; Other control and address inputs are
; Other control and address inputs are
.,
OUT
OUT
77
t
RAS
= 0 mA.
= 0 mA.
t
CK
=
512-Mbit Double-Data-Rate-Two SDRAM
t
=
RASmin.
HYB18T512[400/800/160]A[C/F]–[3.7/5]
t
CKmin.
, CKE is HIGH, CS is
,
t
RC
=
I
min.
min.
min.
t
DD
RCmin
;
;
;
Specifications and Conditions
t
t
t
CK
CK
CK
.,
=
t
=
=
RAS
t
t
t
CKmin
CKmin.
CKmin.
=
09112003-SDM9-IQ3P
.;
;
;
Rev. 1.13, 2004-05
Symbol Notes
I
I
I
I
I
I
I
I
I
I
I
I
DD0
DD1
DD2P
DD2N
DD2Q
DD3P(0)
DD3P(1)
DD3N
DD4R
DD4W
DD5B
DD5D
1)2)3)4)5)6)