HYB18T512160A Infineon Technologies AG, HYB18T512160A Datasheet - Page 35

• Manufacturer Part Number: HYB18T512160A
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: Infineon Technologies AG

Mode exit:
As long as the timing parameter
when ODT is turned on or off after exiting these power-
down modes, synchronous timing parameters can be
Figure 16
2.5
The Bank Activate command is issued by holding CAS
and WE high with CS and RAS low at the rising edge of
the clock. The bank addresses BA[1:0] are used to
select the desired bank. The row addresses A0 through
A13 are used to determine which row to activate in the
selected bank for 4 and 8 organised components.
For 16 components row addresses A0 through A12
have to be applied. The Bank Activate command must
be applied before any Read or Write operation can be
executed. Immediately after the bank active command,
the DDR2 SDRAM can accept a read or write command
Data Sheet
CK, CK
CKE
ODT turn-off, tAXPD >= tAXPDmin:
ODT turn-off, tAXPD < tAXPDmin:
ODT turn-on, tAXPD >= tAXPDmin:
ODT turn-on, tAXPD < tAXPDmin:
timings apply
timings apply
timings apply
timings apply
Synchronous
Asynchronous
Asynchronous
Synchronou s
ODT Mode exit Timing Diagram
Bank Activate Command
T
0
t
IS
T
1
t
AXPD, min
is satisfied
T
5
tAXPD
ODT
ODT
ODT
ODT
T
6
35
applied. If
parameters apply.
(with or without Auto-Precharge) on the following clock
cycle. If a R/W command is issued to a bank that has
not satisfied the
latency must be programmed into the device to delay
the R/W command which is internally issued to the
device. The additive latency value must be chosen to
assure
3 and 4 are supported. Once a bank has been activated
it must be precharged before another Bank Activate
command can be applied to the same bank. The bank
active and precharge times are defined as
512-Mbit Double-Data-Rate-Two SDRAM
t
t
IS
IS
HYB18T512[400/800/160]A[C/F]–[3.7/5]
Rtt
T
7
t
RCD, min
t
AXPD, min
tAONPDmax
t
Rtt
t
is satisfied. Additive latencies of 0, 1, 2,
IS
IS
t
T
8
RCD, min
is not satisfied, asynchronous timing
tAOFPDmax
specification, then additive
tAOND
tAOFD
T
9
Functional Description
09112003-SDM9-IQ3P
Rev. 1.13, 2004-05
Rtt
T10
t
RAS
Rtt
and
ODT04
t
RP
,