HYB18T512160A Infineon Technologies AG, HYB18T512160A Datasheet - Page 16

• Manufacturer Part Number: HYB18T512160A
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: Infineon Technologies AG

1.5
Table 6
Configuration
Number of Banks
Bank Address
Auto-Precharge
Row Address
Column Address
Number of Column Address Bits 11
Number of I/Os
Page Size [Bytes]
1) Refered to as
2) Refered to as ’org’
3)
1.6
Table 7
Symbol
CK, CK
CKE
CS
ODT
RAS, CAS, WE
Data Sheet
PageSize
512Mbit DDR2 Addressing
512 Mbit DDR2 Addressing
Input/Output Functional Description
Input/Output Functional Description
=
’colbits’
2
colbits
Type
Input
Input
Input
Input
Input
org
------- -
8
Function
Clock: CK and CK are differential clock inputs. All address and control inputs are
sampled on the crossing of the positive edge of CK and negative edge of CK. Output
(read) data is referenced to the crossing of CK and CK (both directions of crossing).
Clock Enable: CKE high activates and CKE low deactivates internal clock signals and
device input buffers and output drivers. Taking CKE low provides Precharge Power-
Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active
in any bank). CKE is synchronous for power down entry and exit and for self-refresh
entry. Input buffers excluding CKE are disabled during self-refresh. CKE is used
asynchronously to detect self-refresh exit condition. Self-refresh termination itself is
synchronous. After
sequence, it must be maintained for proper operation of the CKE receiver. For proper
self-refresh entry and exit,
maintained high throughout read and write accesses. Input buffers, excluding CK, CK,
ODT and CKE are disabled during power-down.
Chip Select: All commands are masked when CS is registered high. CS provides for
external rank selection on systems with multiple ranks. CS is considered part of the
command code.
On Die Termination: ODT (registered high) enables termination resistance internal to
the DDR2 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and
DM signal for 4 and DQ, DQS, DQS, RDQS, RDQS and DM for 8 configurations.
For 16 configuration ODT is applied to each DQ, UDQS, UDQS, LDQS, LDQS, UDM
and LDM signal. The ODT pin will be ignored if the EMRS(1) is programmed to disable
ODT.
Command Inputs: RAS, CAS and WE (along with CS) define the command being
entered
128 Mb x 4
4
BA[1:0]
A10 / AP
A[13:0]
A11, A[9:0]
4
1024 (1K)
Bytes
V
REF
has become stable during power-on and initialisation
V
16
REF
must be maintained to this input. CKE must be
64 Mb x 8
4
BA[1:0]
A10 / AP
A[13:0]
A[9:0]
10
8
1024 (1K)
512-Mbit Double-Data-Rate-Two SDRAM
HYB18T512[400/800/160]A[C/F]–[3.7/5]
32 Mb x 16
4
BA[1:0]
A10 / AP
A[12:0]
A[9:0]
10
16
2048 (2K)
09112003-SDM9-IQ3P
Rev. 1.13, 2004-05
Note
1)
2)
3)
Overview