HYB18T512160A Infineon Technologies AG, HYB18T512160A Datasheet - Page 24

• Manufacturer Part Number: HYB18T512160A
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: Infineon Technologies AG

Data Sheet
MR
Mode Register Definition
1) A13 is only available for 4 and 8 configuration.
Field Bits
BL
BT
CL
TM
DLL
WR
PD
1) w = write only register bits
2) CAS Latency 2 is optional for Jedec compliant devices. This option is implemented in this device but is neither tested nor
BA1
0
reg. addr
guaranteed.
[2:0]
3
[6:4]
7
8
[11:9] w
12
BA0
0
Type
w
w
w
w
w
w
A13
0
1)
1)
Description
Burst Length
Number of sequential bits per DQ related to one read/write command.
010 4
011 8
Burst Type
See
0
1
CAS Latency
Number of clock cycles from read command to first data valid window; see
Note: All other bit combinations are RESERVED.
010 2
011 3
100 4
101 5
Test Mode
0
1
DLL Reset
Reset of DLL is required after application of a stable clock; see .
0
1
Write Recovery
Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is
calculated by dividing
The mode register must be programmed to fulfill the minimum requirement for the
analogue
Note: All other bit combinations are RESERVED.
001 2
010 3
011 4
100 5
101 6
Active Power-Down Mode Select
0
1
A12
PD
w
Table 12
Sequential
Interleaved
Normal mode
Vendor specific test mode
No
Yes
WR[cycles]
Fast exit (use
Slow exit (use
A11
2)
t
WR
timing.
for internal address sequence of low order address bits; see
A10
WR
w
t
WR
t
t
XARD
WR
XARDs
(ns) /
A9
t
WR
min
)
(BA[1:0] = 00
(in ns) by
)
t
CK
is determined by
DLL
A8
(ns)
w
24
TM
t
A7
CK
w
512-Mbit Double-Data-Rate-Two SDRAM
HYB18T512[400/800/160]A[C/F]–[3.7/5]
(in ns) and rounding up to the next integer:
B
)
A6
t
CK,max
CL
A5
w
and
WR
A4
max
is determined by
BT
Functional Description
A3
w
09112003-SDM9-IQ3P
Rev. 1.13, 2004-05
A2
Chapter
Chapter
A1
BL
w
t
CK,min
2.6.2.
2.6.1.
A0
.