HYB18T512160A Infineon Technologies AG, HYB18T512160A Datasheet - Page 31

• Manufacturer Part Number: HYB18T512160A
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: Infineon Technologies AG

2.4
On-Die Termination (ODT) is a new feature on DDR2
components that allows a DRAM to turn on/off
termination resistance for each DQ, DQS, DQS, DM for
the same pin), RDQS for 8 configuration via the ODT
control pin. DQS is terminated only when enabled in the
EMRS(1) by address bit A10 = 0. For 8 configuration
RDQS is only terminated, when enabled in the
EMRS(1) by address bits A10 = 0 and A11 = 1.
For 16 configuration ODT is applied to each DQ,
UDQS, UDQS, LDQS, LDQS, UDM and LDM signal via
Figure 12
Switch sw1 or sw2 is enabled by the ODT pin. Selection
between sw1 or sw2 is determined by “Rtt (nominal)” in
EMRS(1) address bits A6 & A2.
Data Sheet
4 and DQ, DQS, DQS, DM, RDQS (DM/RDQS share
On-Die Termination (ODT)
Functional Representation of ODT
DRAM
Buffer
Input
VDDQ
VSSQ
Rval1
Rval1
sw1
sw1
31
the ODT control pin. UDQS and LDQS are terminated
only when enabled in the EMRS(1) by address bit
A10 = 0.
The ODT feature is designed to improve signal integ-
rity of the memory channel by allowing the DRAM con-
troller
resistance for any or all DRAM devices.
The ODT function can be used for all active and
standby modes. ODT is turned off and not supported in
Self-Refresh mode.
Target Rtt = 0.5
The ODT pin will be ignored if the Extended Mode
Register (EMRS(1)) is programmed to disable ODT.
VDDQ
VSSQ
512-Mbit Double-Data-Rate-Two SDRAM
HYB18T512[400/800/160]A[C/F]–[3.7/5]
Rval2
sw2
Rval2
sw2
to
independently
Rval1 or 0.5
Input
Pin
turn
Functional Description
09112003-SDM9-IQ3P
Rval2.
on/off
Rev. 1.13, 2004-05
termination