CS8427 Cirrus Logic, CS8427 Datasheet - Page 47

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CS8427

Manufacturer Part Number
CS8427
Description
96 kHz Digital Audio Interface Transceiver
Manufacturer
Cirrus Logic
Datasheet

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16.4 Synchronization of Multiple CS8427s
The serial audio output ports of multiple CS8427s
can be synchronized if all devices share the same
master clock, OSCLK, OLRCK, and RST line and
leave the reset state on the same master clock fall-
ing edge. Either all the ports need to be in slave
mode, or one can be set as a master.
Multiple AES3 transmitters can be synchronized if
all devices share the same master clock, TCBL, and
RST signals and leave the reset state on the same
master clock falling edge. The TCBL pin is used to
synchronize multiple CS8427 AES3 transmitters at
the channel status block boundaries. One CS8427
must have its TCBL set to master; the others must
DS477PP3
be set to slave TCBL. Alternatively, TCBL can be
derived from external logic, in which case all the
CS8427 devices should be set to slave TCBL.
CS8427
47

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