CS8427 Cirrus Logic, CS8427 Datasheet - Page 37

• Manufacturer Part Number: CS8427
• Description: 96 kHz Digital Audio Interface Transceiver
• Manufacturer: Cirrus Logic

12.15 Receiver Error Mask (11h)
The bits in this register serve as masks for the corresponding bits of the Receiver Error register. If a mask bit is set
to 1, the error is unmasked, meaning that its occurrence will appear in the receiver error register, will affect the RERR
pin, will affect the RERR interrupt, and will affect the current audio sample according to the status of the HOLD bit.
If a mask bit is set to 0, the error is masked, meaning that its occurrence will not appear in the receiver error register,
will not affect the RERR pin, will not affect the RERR interrupt, and will not affect the current audio sample. The
CCRC and QCRC bits behave differently from the other bits: they do not affect the current audio sample even when
unmasked. This register defaults to 00h.
12.16 Channel Status Data Buffer Control (12h)
BSEL - Selects the data buffer register addresses to contain User data or Channel Status data
CBMR - Control for the first 5 bytes of channel status “E” buffer
DETCI - D to E C-data buffer transfer inhibit bit.
EFTCI - E to F C-data buffer transfer inhibit bit.
CAM - C-data buffer control port access mode bit
CHS - Channel select bit
DS477PP3
7
0
7
0
Default = ‘0’
0 - Data buffer address space contains Channel Status data
1 - Data buffer address space contains User data
Default = ‘0’
0 - Allow D to E buffer transfers to overwrite the first 5 bytes of channel status data
1 - Prevent D to E buffer transfers from overwriting first 5 bytes of channel status data
Default = ‘0’
0 - Allow C-data D to E buffer transfers
1 - Inhibit C-data D to E buffer transfers
Default = ‘0’
0 - Allow C-data E to F buffer transfers
1 - Inhibit C-data E to F buffer transfers
Default = ‘0’
0 - One byte mode
1 - Two byte mode
Default = ‘0’
0 - Channel A information is displayed at the EMPH pin and in the receiver channel
1 - Channel B information is displayed at EMPH pin and in the receiver channel
status register. Channel A information is output during control port reads when
CAM is set to 0 (One Byte Mode)
status register. Channel B information is output during control port reads when
CAM is set to 0 (One Byte Mode)
QCRCM
6
6
0
CCRCM
BSEL
5
5
UNLOCKM
CBMR
4
4
DETCI
VM
3
3
CONFM
EFTCI
2
2
BIPM
CAM
1
1
CS8427
PARM
CHS
0
0
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