CS8427 Cirrus Logic, CS8427 Datasheet - Page 13

• Manufacturer Part Number: CS8427
• Description: 96 kHz Digital Audio Interface Transceiver
• Manufacturer: Cirrus Logic

EIAJ CP-1201 standard is available from the Japa-
nese Electronics Bureau.
Crystal Application Note AN22: Overview of Dig-
ital Audio Interface Data Structures contains a use-
ful tutorial on digital audio specifications, but it
should not be considered a substitute for the stan-
dards.
The paper An Understanding and Implementation
of the SCMS Serial Copy Management System for
Digital Audio Transmission, by Clifton Sanchez, is
an excellent tutorial on SCMS. It is available from
the AES as preprint 3518.
3.5
See Crystal Application Note 159: PLL Filter Op-
timization for the CS8415A, CS8420, and CS8427
by Patrick Muyshondt and Stuart Dudley Dimond
III for a tutorial on the CS8427 Phase-Locked-
Loop. This document gives equations for selecting
the proper PLL filter and guidelines on laying out
the PC board for the best performance.
4. DATA I/O FLOW AND CLOCKING
The CS8427 can be configured for several connec-
tivity alternatives, called data flows.
“Software Mode Audio Data Flow Switching Op-
tions” on page 20
along with the control register bits which control
the switches; this drawing only shows the audio
data paths for simplicity. This drawing only shows
the audio data paths for simplicity.
the internal clock routing and the associated control
register bits. The clock routing constraints deter-
mine which data routing options are actually us-
able. Users should note that not all the possible data
flow switch setting combinations are valid, because
of the clock distribution architecture.
The AESBP switch, shown in
TTL level bi-phase mark encoded data stream con-
nected to RXP to be routed to the TXP and TXN
DS477PP3
OPTIONS
PLL Applications Note
shows the data flow switching,
Figure
Figure 10
9, allows a
Figure 9.
shows
pin drivers. The TXOFF switch causes the TXP
and TXN outputs to be driven to ground.
There are two possible clock sources. The first,
designated the recovered clock, is the output of the
PLL, and is output through the RMCK pin. The in-
put to the PLL can be either the incoming AES3
data stream or the ILRCK word rate clock from the
serial audio input port. The second clock is input
through the OMCK pin and would normally be a
crystal derived stable clock. The Clock Source
Control Register bits determine which clock is used
to operate the CS8427.
The CS8427 has another constraint related to the
state machine that governs the startup of the part.
The startup state machine doesn’t complete its pro-
cess until the PLL has locked unless one is in the
transmitter dataflow (See
quence of this is that the transmitter will not trans-
mit until the PLL has locked. If you wish to use the
part in transceiver mode and this constraint is a
problem, there is a work around. Start the part up in
its default configuration and allow the PLL to lock
to a signal on the ILRCK pin, then without stopping
the part, reconfigure it to the transceiver mode.
By studying the following drawings and appropri-
ately setting the Data Flow Control and Clock
Source Control register bits, the CS8427 can be
configured to fit a variety of customer require-
ments. Please note that applications implementing
both the Serial Audio Output Port and the AES3
Transmitter must operate at the same sample rate
because they are both controlled by the same clock
source.
Figure 11
PLL generated recovered clock.
trates a standard AES3 receiver function.
13
without PLL.
transmitter function with PLL.
shows a standard AES3 transmitter function
shows the entire data path clocked by the
Figure 14
shows a standard AES3
Figure
Figure 12
12). The conse-
CS8427
Figure
illus-
13