CS8427 Cirrus Logic, CS8427 Datasheet - Page 16

• Manufacturer Part Number: CS8427
• Description: 96 kHz Digital Audio Interface Transceiver
• Manufacturer: Cirrus Logic

7.
A special mode is available that allows the clock
that is being input through the OMCK pin to be out-
put through the RMCK pin. This feature is con-
trolled by the SWCLK bit in control register 1.
When the PLL loses lock, the frequency of the
VCO drops to 300 kHz. The SWCLK function al-
lows the clock from RMCK to be used as a clock in
the system without any disruption when input is re-
moved from the Receiver. This clock switching is
done glitch free. None of the internal circuitry that
is clocked from the PLL is driven by the OMCK
being output from RMCK.
8.
The PLL behavior is affected by the external filter
component values.
ed configuration of the two capacitors and one re-
sistor required. Two alternate sets of component
values are recommended, depending on the re-
quirements of the application (see
page
dates input sample rates of 32 kHz to 108 Hz with
no component changes. It has the highest corner
frequency jitter attenuation curve, and takes the
shortest time to lock. The alternate component set,
called “medium” allows the lowest input sample
rate to be 8 kHz, and increases the lock time of the
PLL. Lock times are worst case for an Fsi transition
of 96 kHz.
8.1
While decoding the incoming AES3 data stream,
the CS8427 can identify several kinds of error, in-
dicated in the Receiver Error register. The UN-
LOCK bit indicates whether the PLL is locked to
the incoming AES3 data. The V bit reflects the cur-
rent validity bit status. The BIP (bi-phase) error bit
indicates an error in incoming bi-phase coding. The
PAR (parity) bit indicates a received parity error.
The error bits are "sticky": they are set on the first
occurrence of the associated error and will remain
16
18). The default set, called “fast”, accommo-
OMCK OUT ON RMCK
PLL EXTERNAL COMPONENTS
Error Reporting and Hold Function
Figure 5
shows the recommend-
Table 1 on
set until the user reads the register through the con-
trol port. This enables the register to log all un-
masked errors that occurred since the last time the
register was read.
The Receiver Error Mask register allows masking
of individual errors. The bits in this register serve
as masks for the corresponding bits of the Receiver
Error Register. If a mask bit is set to 1, the error is
unmasked, which implies the following: its occur-
rence will be reported in the receiver error register,
induce a pulse on RERR, invoke the occurrence of
a RERR interrupt, and affect the current audio sam-
ple according to the status of the HOLD bits. The
HOLD bits allow a choice of holding the previous
sample, replacing the current sample with zero
(mute), or not changing the current audio sample. If
a mask bit is set to 0, the error is masked, which im-
plies the following: its occurrence will not be re-
ported in the receiver error register, will not induce
a pulse on RERR or generate a RERR interrupt, and
will not affect the current audio sample. The QCRC
and CCRC errors do not affect the current audio
sample, even if unmasked
8.2
The first two bytes of the Channel Status block are
decoded into the Receiver Channel Status register.
The setting of the CHS bit in the Channel Status
Data Buffer Control register determines whether
the channel status decodes are from the A channel
(CHS = 0) or B channel (CHS = 1).
The PRO (professional) bit is extracted directly.
For consumer data, the COPY (copyright) bit is ex-
tracted, and the category code and L bits are decod-
ed to determine SCMS status, indicated by the
ORIG (original) bit. If the category code is set to
General on the incoming AES3 stream, copyright
will always be indicated even when the stream in-
dicates no copyright. Finally, the AUDIO bit is ex-
tracted and used to set an AUDIO indicator, as
described in the Non-Audio Auto-Detection sec-
tion below.
Channel Status Data Handling
CS8427
DS477PP3