CS8427 Cirrus Logic, CS8427 Datasheet - Page 31

• Manufacturer Part Number: CS8427
• Description: 96 kHz Digital Audio Interface Transceiver
• Manufacturer: Cirrus Logic

12.4 Clock Source Control (4h)
This register configures the clock sources of various blocks. In conjunction with the Data Flow Control register, var-
ious Receiver/Transmitter/Transceiver modes may be selected.
RUN - Controls the internal clocks, allowing the CS8427 to be placed in a “powered down”, low current consumption,
CLK1:0 - Output side master clock input (OMCK) frequency to output sample rate (Fso) ratio selector. If these bits
OUTC - Output Time Base
INC - Input Time Base Clock Source
RXD1:0 - Recovered Input Clock Source
12.5 Serial Audio Input Port Data Format (5h)
SIMS - Master/Slave Mode Selector
DS477PP3
state.
are changed during normal operation, then always stop the CS8427 first (RUN = 0), write the new value, then start
the CS8427 (RUN = 1).
SIMS
7
0
7
Default = ‘0’
0 - Internal clocks are stopped. Internal state machines are reset. The fully static
1 - Normal part operation. This bit must be written to the 1 state to allow the CS8427
Default = ‘00’
00 - OMCK frequency is 256 * Fso
01 - OMCK frequency is 384 * Fso
10 - OMCK frequency is 512 * Fso
11 - Reserved
Default = ‘0’
0 - OMCK input pin, modified by the selected divide ratio bits CLK1:0.
1 - Recovered Input Clock
Default = ‘0’
0 - Recovered Input Clock
1 - OMCK input pin, modified by the selected divide ratio bits CLK1:0.
Default = ‘00’
00 - 256 * Fsi, where Fsi is derived from the ILRCK pin (only possible when the
01 - 256 * Fsi, where Fsi is derived from the AES3 input frame rate
10 - Bypass the PLL and apply an external 256 * Fsi clock through the RMCK pin. The AES3
11 - Reserved.
Default = ‘0’
0 - Serial audio input port is in slave mode
1 - Serial audio input port is in master mode
control port is operational, allowing registers to be read or changed. Reading and
writing the U and C data buffers is not possible. Power consumption is low.
to begin operation. All input clocks should be stable in frequency and phase when
RUN is set to 1.
serial audio input port is in slave mode)
receiver is held in synchronous reset. This setting is useful to prevent UNLOCK
interrupts when using an external RMCK and inputting data through the serial audio input port.
SISF
RUN
6
6
SIRES1
CLK1
5
5
SIRES0
CLK0
4
4
SIJUST
OUTC
3
3
SIDEL
INC
2
2
SISPOL
RXD1
1
1
CS8427
SILRPOL
RXD0
0
0
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