CS8427 Cirrus Logic, CS8427 Datasheet - Page 34

• Manufacturer Part Number: CS8427
• Description: 96 kHz Digital Audio Interface Transceiver
• Manufacturer: Cirrus Logic

12.8 Interrupt 2 Status (8h) (Read Only)
For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since the register
was last read. A ”0” means the associated interrupt condition has NOT occurred since the last reading of the register.
Reading the register resets all bits to 0, unless the interrupt mode is set to level and the interrupt source is still true.
Status bits that are masked off in the associated mask register will always be “0” in this register. This register defaults
to 00h.
DETU - D to E U-buffer transfer interrupt. (Block Mode only)
EFTU - E to F U-buffer transfer interrupt. (Block Mode only)
QCH - A new block of Q-subcode data is available for reading.
12.9 Interrupt 1 Mask (9h)
The bits of this register serve as a mask for the Interrupt 1 register. If a mask bit is set to 1, the error is unmasked,
meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is masked,
meaning that its occurrence will not affect the INT pin or the status register. The bit positions align with the corre-
sponding bits in the Interrupt 1 register. This register defaults to 00h.
12.10 Interrupt 1 Mode MSB (Ah) & Interrupt 1 Mode LSB (Bh)
The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. There are three ways to
set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode, the INT pin be-
comes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT pin becomes active
on the removal of the interrupt condition. In Level active mode, the INT interrupt pin becomes active during the in-
terrupt condition. Be aware that the active level(Active High or Low) only depends on the INT[1:0] bits. These regis-
ters default to 00.
34
TSLIPM
TSLIP1
TSLIP0
7
0
7
7
The source of this bit is true during the D to E buffer transfer in the U bit buffer management process.
The source of this bit is true during the E to F buffer transfer in the U bit buffer management process.
The data must be completely read within 588 AES3 frames after the interrupt occurs to avoid corruption
of the data by the next block.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
OSLIPM
OSLIP1
OSLIP0
6
0
6
6
5
5
5
0
0
0
0
4
0
4
0
4
0
0
DETU
3
3
0
3
0
0
DETCM
DETC1
DETC0
EFTU
2
2
2
EFTCM
EFTC1
EFTC0
QCH
1
1
1
CS8427
DS477PP3
RERRM
RERR1
RERR0
0
0
0
0