CS8427 Cirrus Logic, CS8427 Datasheet - Page 33

• Manufacturer Part Number: CS8427
• Description: 96 kHz Digital Audio Interface Transceiver
• Manufacturer: Cirrus Logic

SOJUST - Justification of SDOUT data relative to OLRCK
SODEL - Delay of SDOUT data relative to OLRCK, for left-justified data formats
SOSPOL - OSCLK clock polarity
SOLRPOL - OLRCK clock polarity
12.7 Interrupt 1 Status (7h) (Read Only)
For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since the register
was last read. A ”0” means the associated interrupt condition has NOT occurred since the last reading of the register.
Reading the register resets all bits to 0, unless the interrupt mode is set to level and the interrupt source is still true.
Status bits that are masked off in the associated mask register will always be “0” in this register. This register defaults
to 00h.
TSLIP - AES3 transmitter source data slip interrupt.
OSLIP - Serial audio output port data slip interrupt.
DETC - D to E C-buffer transfer interrupt.
EFTC - E to F C-buffer transfer interrupt.
RERR - A receiver error has occurred.
DS477PP3
TSLIP
7
Default = ‘0’
0 - Left-justified
1 - Right-justified (master mode only)
Default = ‘0’
0 - MSB of SDOUT data occurs in the first OSCLK period after the OLRCK edge
1 - MSB of SDOUT data occurs in the second OSCLK period after the OLRCK edge
Default = ‘0’
0 - SDOUT transitions occur on falling edges of OSCLK
1 - SDOUT transitions occur on rising edges of OSCLK
Default = ‘0’
0 - SDOUT data is for the left channel when OLRCK is high
1 - SDOUT data is for the right channel when OLRCK is high
In data flows where OMCK, which clocks the AES3 transmitter, is asynchronous to the data source, this
bit will go high every time a data sample is dropped or repeated. When TCBL is an input, this bit will go
high on receipt of a new TCBL signal.
When the serial audio output port is in slave mode, and OLRCK is asynchronous to the port data source,
this bit will go high every time a data sample is dropped or repeated.
The source for this bit is true during the D to E buffer transfer in the C bit buffer management process.
The source for this bit is true during the E to F buffer transfer in the C bit buffer management process.
The Receiver Error register may be read to determine the nature of the error which caused the interrupt.
OSLIP
6
5
0
4
0
3
0
DETC
2
EFTC
1
CS8427
RERR
0
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