CS8427 Cirrus Logic, CS8427 Datasheet - Page 46

• Manufacturer Part Number: CS8427
• Description: 96 kHz Digital Audio Interface Transceiver
• Manufacturer: Cirrus Logic

16. APPLICATIONS
16.1 Reset, Power Down and Start-up
When RST is low, the CS8427 enters a low power
mode and all internal states are reset, including the
control port and registers, and the outputs are mut-
ed. When RST is high, the control port becomes
operational and the desired settings should be load-
ed into the control registers. Writing a 1 to the RUN
bit will then cause the part to leave the low power
state and begin operation. After the PLL has set-
tled, the AES3 and serial audio outputs will be en-
abled.
Some options within the CS8427 are controlled by
a start-up mechanism. During the reset state, some
of the output pins are reconfigured internally to be
inputs. Immediately upon exiting the reset state, the
level of these pins is sensed. The pins are then
switched to be outputs. This mechanism allows
output pins to be used to set alternative modes in
the CS8427 by connecting a 47kΩ resistor to be-
tween the pin and either VL+ (HI) or DGND (LO).
For each mode, every start-up option select pin
MUST have an external pull-up or pull-down resis-
tor. In software mode, the only start-up option pin
is EMPH, which is used to set a chip address bit for
the control port in Two-Wire mode. Hardware
modes use many start-up options, which are de-
tailed in the hardware definition section at the end
of this data sheet.
16.2 ID Code and Revision Code
The CS8427 has a register that contains a four bit
code to indicate that the addressed device is a
CS8427. This is useful when other CS84XX family
46
members are resident in the same system, allowing
common software modules.
The CS8427 four bit revision code is also available.
This allows the software driver for the CS8427 to
identify which revision of the device is in a partic-
ular system, and modify its behavior accordingly.
To allow for future revisions, it is strongly recom-
mend that the revision code is read into a variable
area within the microcontroller, and used wherever
appropriate as revision details become known.
16.3 Power Supply, Grounding, and PCB
For most applications, the CS8427 can be operated
from a single +5 V supply, following normal sup-
ply decoupling practices, see
For applications where the recovered input clock,
output on the RMCK pin, is required to be low jit-
ter, then use a separate, quiet, analog +5 V supply
for VA+, decoupled to AGND. In addition, a sepa-
rate region of analog ground plane around the
FILT, AGND, VA+, RXP, and RXN pins is recom-
mended.
The VL+ supply should be well decoupled with a
0.1 µF capacitor to DGND to minimize AES3
transmitter induced transients.
Extensive use of power and ground planes, ground
plane fill in unused areas and surface mount decou-
pling capacitors are recommended. Decoupling ca-
pacitors should be mounted on the same side of the
board as the CS8427 to minimize inductance ef-
fects, and all decoupling capacitors should be as
close to the CS8427 as possible.
layout
Figure 5 on page
CS8427
DS477PP3
10.