CS8427 Cirrus Logic, CS8427 Datasheet - Page 15

• Manufacturer Part Number: CS8427
• Description: 96 kHz Digital Audio Interface Transceiver
• Manufacturer: Cirrus Logic

6.
The CS8420 includes an AES3 digital audio re-
ceiver and an AES3 digital audio transmitter. A
comprehensive
read/write access to the channel status and user da-
ta. This buffering scheme is described in
dix B: Channel Status and User Data Buffer
Management” on page
6.1 AES3 Receiver
The AES3 receiver accepts and decodes audio and
digital data according to the AES3, IEC60958
(S/PDIF), and EIAJ CP-1201 interface standards.
The receiver consists of a differential input stage,
accessed through pins RXP and RXN, a PLL based
clock recovery circuit, and a decoder which sepa-
rates the audio data from the channel status and
user data.
External components are used to terminate and iso-
late the incoming data cables from the CS8427.
These components are detailed in
External AES3/SPDIF/IEC60958 Transmitter and
Receiver Components” on page
DS477PP3
AES3 RECEIVER
buffering
52.
scheme
50.
“Appendix A:
provides
“Appen-
6.1.1
An on-chip Phase Locked Loop (PLL) is used to re-
cover the clock from the incoming data stream. In
some applications, low jitter in the recovered clock,
presented on the RMCK pin, is important. For this
reason, the PLL has been designed to have good jit-
ter attenuation characteristics, shown in
and
signed to only use the preambles of the AES3
stream to provide lock update information to the
PLL. This results in the PLL being immune to data
dependent jitter effects, since the AES3 preambles
do not vary with the data. The PLL has the ability
to lock onto a wide range of input sample rates with
no external component changes. If the sample rate
of the input subsequently changes, for example in a
varispeed application, the PLL will only track up to
±12.5% from the nominal center sample rate. The
nominal center sample rate is the sample rate that
the PLL first locks onto upon application of an
AES3 data stream or after enabling the CS8427
clocks by setting the RUN control bit. If the 12.5%
sample rate limit is exceeded, the PLL will return
to its wide lock range mode and re-acquire a new
nominal center sample rate.
Figure
PLL, Jitter Attenuation, Varispeed
8. In addition, the PLL has been de-
CS8427
Figure 7
15