CS8427 Cirrus Logic, CS8427 Datasheet - Page 11

• Manufacturer Part Number: CS8427
• Description: 96 kHz Digital Audio Interface Transceiver
• Manufacturer: Cirrus Logic

3. GENERAL DESCRIPTION
The CS8427 is an AES3 transceiver intended to be
used in digital audio systems. Such systems include
digital mixing consoles, effects processors, digital
recorders and computer multimedia systems.
3.1
The CS8427 has the following Audio ports:
•
•
•
•
The Serial Audio ports use a three-wire format.
This consists of a serial audio data stream, a left-
right clock defining the boundaries of the audio
sample frames, and a serial clock signal clocking
the data bits.
A Serial Audio port may operate in either Master or
Slave mode. When a port is a Master, it supplies the
left-right clock and the serial clock to the external
device that is sending or receiving the serial data. A
port in slave mode must have its left-right clock
and its serial clock supplied by an external device
so that it may send or receive serial audio data.
The input sample rate is determined by the stream
applied to the Serial Audio Input or to the AES3
Receiver. A phase-locked-loop recovers RMCK,
the input master clock signal, from the chosen input
stream.
The output from the chip may be through the Serial
Audio Output, the AES3 Transmitter or from both
simultaneously. In some configurations, all audio
ports of the chip may be in use at the same time.
3.2
Besides the functional blocks already described,
the device also has a control port that allows the
user to read and write the control registers that con-
figure the part. The control port is capable of oper-
ating in either SPI or two-wire serial mode. This
DS477PP3
Serial Audio Input Port
Serial Audio Output Port
AES3 or S/PDIF Receiver
AES3 or S/PDIF Transmitter
Audio Input/Output Ports
Serial Control Port
port also has access to buffer memory that allows
the user to control what is transmitted in the Chan-
nel Status and User bits of the outgoing AES3
stream.
The control port is clocked by the serial clock sig-
nal that the user's micro-controller sends it. The
MCU can read and write the registers even when
the RMCK and OMCK clocks are not running. The
Channel Status and User bit buffer memories de-
pend on clocking from RMCK and OMCK. They
will not function unless the clocks are running, and
the RUN bit in the Clock Source Control register is
set.
There is also an interrupt signal associated with the
Serial Control Port and the internal registers. The
format of the interrupt may be chosen by a register
setting. There are two interrupt status registers and
their associated interrupt mask registers.
3.3
The memory architecture consists of three buffers
to handle the Channel Status information, and an-
other three buffers to handle the User bits. The data
recovery logic extracts the Channel Status and User
bits from the AES3 stream and places them in their
respective D buffers. Each buffer contains 384 bits.
This is enough memory to hold a complete block of
Channel Status bits from both A and B channels
and a complete block of User bits.
When the D buffers are full, the chip transfers their
contents into the E buffers. While in the E buffers
the Channel Status and User bits may be read or
written through the control port. This allows the
user to alter them to suit the needs of the applica-
tion. The control bit BSEL, in the Channel Status
Data Buffer Control register, determines whether
the control port has access to the Channel Status
bits or the User bits. The AES3 encoder reads the
Channel Status and User bits from the F buffers and
inserts them into the outgoing AES3 stream. After
the F buffers bits are transmitted, the chip transfers
Channel Status and User bit Memory
CS8427
11