CS8427 Cirrus Logic, CS8427 Datasheet - Page 17

• Manufacturer Part Number: CS8427
• Description: 96 kHz Digital Audio Interface Transceiver
• Manufacturer: Cirrus Logic

If 50/15 µs pre-emphasis is detected, the state of the
EMPH pin is adjusted accordingly.
The encoded channel status bits which indicate
sample word length are decoded according to
AES3-1992 or IEC 60958. Audio data routed to the
serial audio output port is unaffected by the word
length settings; all 24 bits are passed on as re-
ceived.
“Appendix B: Channel Status and User Data Buffer
Management” on page 52
handling of Channel Status and User bit data.
8.3
The incoming user data is buffered in a user acces-
sible buffer. Various automatic modes of re-trans-
mitting received User data are provided. The
Appendix: Channel Status and User Data Buffer
Management describes the overall handling of CS
and U data.
Received User data may also be output to the U pin,
under the control of a control register bit. Depend-
ing on the data flow and clocking options selected,
there may not be a clock available to qualify the U
data output.
If the incoming user data bits have been encoded as
Q-channel subcode, the data is decoded and pre-
sented in ten consecutive register locations. An in-
DS477PP3
User Data Handling
Figure 15
illustrates the timing.
describes the overall
terrupt may be enabled to indicate the decoding of
a new Q-channel block, which may be read through
the control port.
8.4
An AES3 data stream may be used to convey non-
audio data, thus it is important to know whether the
incoming AES3 data stream is digital audio or not.
This information is typically conveyed in channel
status bit 1 (AUDIO), which is extracted automati-
cally by the CS8427. However, certain non-audio
sources, such as AC3 or MPEG encoders, may not
adhere to this convention, and the bit may not be
properly set. The CS8427 AES3 receiver can detect
such non-audio data. This is accomplished by look-
ing for a 96-bit sync code, consisting of 0x0000,
0x0000, 0x0000, 0x0000, 0xF872, and 0x4E1F.
When the sync code is detected, an internal AUTO-
DETECT signal will be asserted. If no additional
sync codes are detected within the next 4096
frames, AUTODETECT will be de-asserted until
another sync code is detected. The AUDIO bit in
the Receiver Channel Status register is the logical
OR of AUTODETECT and the received channel
status bit 1. If non-audio data is detected, the data
is still processed exactly as if it were normal audio.
It is up to the user to mute the outputs as required.
Non-Audio Auto Detection
CS8427
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