MMC2114 MOTOROLA [Motorola, Inc], MMC2114 Datasheet - Page 540

• Manufacturer Part Number: MMC2114
• Description: M CORE Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

External Bus Interface Module (EBI)
20.8 Bus Exception Operation
20.8.1 Transfer Error Termination
20.8.2 Transfer Abort Termination
20.9 Emulation Support
20.9.1 Emulation Chip-Selects (CSE[1:0])
Advance Information
540
Normal bus cycle termination requires the assertion of the TA pin or the
internal transfer acknowledge signal. Minimal bus exception support is
provided by transfer error cycle termination. For transfer error cycle
termination, the external TEA pin or the internal transfer error
acknowledge signal is asserted. Transfer error cycle termination takes
precedence over normal cycle termination, provided TEA assertion
meets its timing constraints.
The internal bus monitor will assert the internal transfer error
acknowledge signal when TA response time is too long, based upon the
BMT[1:0] settings in the Chip Configuration Registers (CCR). See
4.7.3.1 Chip Configuration
External bus cycles which are aborted by the M•CORE, still have the
address, R/W, TC[2:0], TSIZ[1:0], CS (if used), OE (reads only), and
SHS (if used) driven to the external pins.
While in emulation mode or master mode, special emulator chip-selects
(CSE[1:0]) are driven externally to allow internal/external accesses to be
tracked by external hardware See
In emulation mode, all port registers are mapped externally.
CSE[1:0] = 10 whenever any emulated port registers are addressed.
The lower bits of the address bus indicate the register accessed within
the block.
Freescale Semiconductor, Inc.
For More Information On This Product,
External Bus Interface Module (EBI)
Go to: www.freescale.com
Register.
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
Table
20-4.
MOTOROLA