MMC2114 MOTOROLA [Motorola, Inc], MMC2114 Datasheet - Page 403

• Manufacturer Part Number: MMC2114
• Description: M CORE Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
SPE — SPI System Enable Bit
SWOM — SPI Wired-OR Mode Bit
MSTR — Master Bit
CPOL — Clock Polarity Bit
CPHA — Clock Phase Bit
The SPE bit enables the SPI and dedicates SPI port pins [3:0] to SPI
functions. When SPE is clear, the SPI system is initialized but in a
low-power disabled state. Reset clears SPE.
The SWOM bit configures the output buffers of SPI port pins [3:0] as
open-drain outputs. SWOM controls SPI port pins [3:0] whether they
are SPI outputs or general-purpose outputs. Reset clears SWOM.
The MSTR bit selects SPI master mode or SPI slave mode operation.
Reset clears MSTR.
The CPOL bit selects an inverted or non-inverted SPI clock. To
transmit data between SPI modules, the SPI modules must have
identical CPOL values. Reset clears CPOL.
The CPHA bit delays the first edge of the SCK clock. Reset sets
CPHA.
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1 = SPI enabled
0 = SPI disabled
1 = Output buffers of SPI port pins [3:0] open-drain
0 = Output buffers of SPI port pins [3:0] CMOS drive
1 = Master mode
0 = Slave mode
1 = Active-low clock; SCK idles high
0 = Active-high clock; SCK idles low
1 = First SCK edge at start of transmission
0 = First SCK edge 1/2 cycle after start of transmission
Serial Peripheral Interface Module (SPI)
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Serial Peripheral Interface Module (SPI)
Memory Map and Registers
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