MMC2114 MOTOROLA [Motorola, Inc], MMC2114 Datasheet - Page 323

• Manufacturer Part Number: MMC2114
• Description: M CORE Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

16.7 Memory Map and Registers
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
0x00ce_0000
0x00ce_0001
0x00ce_0002
0x00ce_0003
0x00ce_0004
0x00ce_0005
0x00ce_0006
0x00ce_0007
0x00ce_0008
0x00ce_0009
0x00ce_000a
0x00ce_000b
0x00ce_000d
0x00ce_000e
0x00ce_0010
0x00ce_0012
0x00ce_0013
0x00ce_0014
0x00ce_0015
0x00ce_0016
0x00ce_000c
0x00ce_0011
0x00ce_000f
TIM1
Address
NOTE:
0x00cf_0000
0x00cf_0001
0x00cf_0002
0x00cf_0003
0x00cf_0004
0x00cf_0005
0x00cf_0006
0x00cf_0007
0x00cf_0008
0x00cf_0009
0x00cf_000a
0x00cf_000b
0x00cf_000c
0x00cf_000d
0x00cf_000e
0x00cf_0010
0x00cf_0011
0x00cf_0012
0x00cf_0013
0x00cf_0014
0x00cf_0015
0x00cf_0016
0x00cf_000f
TIM2
See
a base address of 0x00ce_0000. Timer 2 has a base address of
0x00cf_0000.
Reading reserved or unimplemented locations returns 0s. Writing to
reserved or unimplemented locations has no effect.
Table 16-2. Timer Modules Memory Map
Freescale Semiconductor, Inc.
Table 16-2
For More Information On This Product,
Timer Modules (TIM1 and TIM2)
Timer Output Compare 3 Mask Register (TIMOC3M)
Timer Output Compare 3 Data Register (TIMOC3D)
Go to: www.freescale.com
Timer Compare Force Register (TIMCFORC)
Timer Toggle-on-Overflow Register (TMTOV)
Timer System Control Register 1 (TIMSCR1)
Timer System Control Register 2 (TIMSCR2)
Timer Channel 0 Register High (TIMC0H)
Timer Channel 1 Register High (TIMC1H)
Timer Channel 2 Register High (TIMC2H)
Timer Channel 3 Register High (TIMC3H)
Timer Counter Register High (TIMCNTH)
Timer Channel 0 Register Low (TIMC0L)
Timer Channel 1 Register Low (TIMC1L)
Timer Channel 2 Register Low (TIMC2L)
for a memory map of the two timer modules. Timer 1 has
Timer Counter Register Low (TIMCNTL)
Timer Interrupt Enable Register (TIMIE)
Timer IC/OC Select Register (TIMIOS)
Timer Control Register 1 (TIMCTL1)
Timer Control Register 2 (TIMCTL2)
Timer Flag Register 1 (TIMFLG1)
Timer Flag Register 2 (TIMFLG2)
Reserved
Reserved
Bits 7–0
(2)
(2)
Timer Modules (TIM1 and TIM2)
Memory Map and Registers
Advance Information
Access
²
²
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
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