MMC2114 MOTOROLA [Motorola, Inc], MMC2114 Datasheet - Page 216
![no-image](/images/no-image-200.jpg)
MMC2114
Manufacturer Part Number
MMC2114
Description
M CORE Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MMC2114.pdf
(654 pages)
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Second Generation FLASH for M•CORE (SGFM)
10.7.1.3 SGFM Test Register
Advance Information
216
NOTE:
Address: 0x00d0_0004
DIVLD — Clock Divider Loaded Bit
PRDIV8 — Enable Prescaler Divide by 8 Bit
DIV[5:0] — Clock Divider Field
SGFMCLKD must be written with an appropriate value before
programming or erasing the FLASH array. Refer to
SGFMCLKD
The SGFM Test Register (SGFMTST) is unbanked and is used only for
factory testing.
Accesses to SGFMTST when not in test mode will result in a cycle
termination transfer error.
Reset:
Read:
Write:
The combination of PRDIV8 and DIV[5:0] effectively divides the
SGFM input clock down to a frequency between 150 kHz and
200 kHz. The frequency range of the SGFM clock is 150 kHz to
102.4 MHz.
Freescale Semiconductor, Inc.
Second Generation FLASH for M•CORE (SGFM)
For More Information On This Product,
1 = SGFMCLKD has been written since the last reset.
0 = SGFMCLKD has not been written.
1 = Enables a prescaler that divides the SGFM clock by 8 before it
0 = The SGFM clock is fed directly into the SGFMCLKD divider.
RSVD7
Bit 7
enters the SGFMCLKD divider.
0
Figure 10-5. SGFM Test Register (SGFMTST)
Go to: www.freescale.com
Register.
= Reserved
RSVD6
6
0
RSVD5
5
0
RSVD4
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
4
0
3
0
0
10.8.3.1 Setting the
2
0
0
RSVD1
1
0
MOTOROLA
RSVD0
Bit 0
0
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