MMC2114 MOTOROLA [Motorola, Inc], MMC2114 Datasheet - Page 161

• Manufacturer Part Number: MMC2114
• Description: M CORE Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

6.4.8 FLASH
6.4.9 Queued Analog-to-Digital Converter (QADC)
6.4.10 Watchdog Timer
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
The FLASH is in a low-power state if not being accessed. No recovery
time is required after exit from any low-power mode.
Setting the queued analog-to-digital converter (QADC) STOP bit
(QSTOP) will disable the QADC.
The QADC is unaffected by either wait or doze mode and may generate
an interrupt to exit these modes.
Low-power stop mode (or setting the QSTOP bit), immediately freezes
operation, register values, state machines, and external pins. This stops
the clock signals to the digital electronics of the module and eliminates
the quiescent current draw of the analog electronics. Any conversion
sequences in progress are stopped. Exit from low-power stop mode (or
clearing the QSTOP bit), returns the QADC to operation from the state
prior to stop mode entry, but any conversions in progress are undefined
and the QADC requires recovery time (t
Characteristics) to stabilize the analog circuits before new conversions
can be performed.
In stop mode (or in wait/doze mode, if so programmed), the watchdog
ceases operation and freezes at the current value.When exiting these
modes, the watchdog resumes operation from the stopped value. It is
the responsibility of software to avoid erroneous operation.
When not stopped, the watchdog may generate a reset to exit the
low-power modes.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Power Management
Peripheral Behavior in Low-Power Modes
SR
in
23.9 QADC Electrical
Advance Information
Power Management
161