MMC2114 MOTOROLA [Motorola, Inc], MMC2114 Datasheet - Page 470

• Manufacturer Part Number: MMC2114
• Description: M CORE Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Queued Analog-to-Digital Converter (QADC)
19.8.8.3 Left-Justified Unsigned Result Register (LJURR)
19.9 Functional Description
19.9.1 Result Coherency
Advance Information
470
Address: 0x00ca_0380 through 0x00ca_03fe
Reset:
Reset:
Read:
Read:
Write:
Write:
RESULT[15:6] — Result Field
This subsection provides a functional description of the QADC.
The QADC supports byte and half-word reads and writes across a 16-bit
data bus interface. All conversion results are stored in half-word
registers, and the QADC does not allow more than one result register to
be read at a time. For this reason, the QADC does not guarantee read
coherency.
Specifically, this means that while the QADC is operating, the data in the
result registers can change from one read to the next. Simply initiating a
read of one result register will not prevent another from being updated
with a new conversion result.
Thus, to read any given number of result registers coherently, the queue
or queues capable of modifying these registers must be inactive. This
can be guaranteed by system operating conditions (such as, known
completion of a software-initiated queue single-scan or no possibility of
an externally triggered/gated queue scan) or by simply disabling the
queues (writing MQ1 and/or MQ2 to 0).
Figure 19-17. Left-Justified Unsigned Result Register (LJURR)
The conversion result is unsigned, left-justified data.
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Bit 15
Bit 7
RESULT
Go to: www.freescale.com
= Writes have no effect and the access terminates without a transfer error exception.
14
6
13
5
0
0
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
12
4
0
0
RESULT
11
3
0
0
10
2
0
0
9
1
0
0
MOTOROLA
Bit 8
Bit 0
0
0