M30280F6HP RENESAS [Renesas Technology Corp], M30280F6HP Datasheet - Page 96

• Manufacturer Part Number: M30280F6HP
• Description: 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES
• Manufacturer: RENESAS [Renesas Technology Corp]

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9.4 Interrupt Sequence
e
E
1
. v
J
6
Figure 9.5 Time Required for Executing Interrupt Sequence
0
An interrupt sequence (the device behavior from the instant an interrupt is accepted to the instant the
interrupt routine is executed) is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
The CPU behavior during the interrupt sequence is described below. Figure 9.5 shows time required for
executing the interrupt sequence.
(1) The CPU gets interrupt information (interrupt number and interrupt request priority level) by reading
(2) The FLG register immediately before entering the interrupt sequence is saved to the CPU’s internal
(3) The I, D and U flags in the FLG register become as follows:
(4) The CPU’s internal temporary register
(5) The PC is saved to the stack.
(6) The interrupt priority level of the accepted interrupt is set in the IPL.
(7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC.
After the interrupt sequence is completed, the processor resumes executing instructions from the start
address of the interrupt routine.
Note 1: This register cannot be used by user.
C
2
9
NOTES:
2 /
The I flag is cleared to “0” (interrupts disabled).
The D flag is cleared to “0” (single-step interrupt disabled).
The U flag is cleared to “0” (ISP selected).
Address bus
0 .
B
However, the U flag does not change state if an INT instruction for software interrupt Nos. 32 to 63 is
executed.
the address 00000
requested).
temporary register
0
CPU clock
0
8
1. The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue
2. When the stack is in the internal RAM, the WR signal indicates the write timing by changing high-level to low-level.
0
Data bus
G
4
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buffer is ready to accept instructions.
7
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0 -
. n
WR
u
RD
2
3
p
0
, 1
(2)
0
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2
0
1
0
6
7
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1
2 /
Address
, 8
(1)
0000
16
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information
2
.
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. Then it clears the IR bit for the corresponding interrupt to “0” (interrupt not
Interrupt
16
1
6
3
C
2 /
f o
8
3
4
) B
8
5
Indeterminate
Indeterminate
Indeterminate
5
(1)
6
is saved to the stack.
(1)
7
(1)
(1)
8
SP-2
9
contents
SP-2
10
SP-4
11
contents
SP-4
12
13
vec
contents
vec
14
vec+2
15
contents
vec+2
16
17
PC
9. Interrupts
18