M30280F6HP RENESAS [Renesas Technology Corp], M30280F6HP Datasheet - Page 89

• Manufacturer Part Number: M30280F6HP
• Description: 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES
• Manufacturer: RENESAS [Renesas Technology Corp]

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9.1.2 Hardware Interrupts
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Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts.
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9.1.2.1 Special Interrupts
9.1.2.2 Peripheral Function Interrupts
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Special interrupts are non-maskable interrupts.
9.1.2.1.1 NMI Interrupt
9.1.2.1.2 DBC Interrupt
9.1.2.1.3 Watchdog Timer Interrupt
9.1.2.1.4 Oscillation Stop and Re-oscillation Detection Interrupt
9.1.2.1.5 Low Voltage Detection Interrupt
9.1.2.1.6 Single-step Interrupt
9.1.2.1.7 Address Match Interrupt
Peripheral function interrupts are maskable interrupts and generated by the microcomputer's internal
functions. The interrupt sources for peripheral function interrupts are listed in Table 9.2 Relocatable
Vector Tables. For details about the peripheral functions, refer to the description of each peripheral
function in this manual.
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An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details
about the NMI interrupt, refer to the section 9.7 NMI interrupt.
This interrupt is exclusively for debugger, do not use in any other circumstances.
Generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to initialize
the watchdog timer. For details about the watchdog timer, refer to 10. Watchdog Timer.
Generated by the oscillation stop and re-oscillation detection function. For details about the oscilla-
tion stop and re-oscillation detection function, refer to the section 7. Clock Generating Circuit.
Generated by the voltage detection circuit. For details about the voltage detection circuit, refer to 5.5
Voltage Detection Circuit.
Do not normally use this interrupt because it is provided exclusively for use by development support
tools.
An address match interrupt is generated immediately before executing the instruction at the address
indicated by the RMAD0 or RMAD1 register, if the corresponding enable bit (the AIER0 or AIER1bit
in the AIER register) is set to “1”. For details about the address match interrupt, refer to 9.9 Address
Match Interrupt.
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9. Interrupts