M30280F6HP RENESAS [Renesas Technology Corp], M30280F6HP Datasheet - Page 227

• Manufacturer Part Number: M30280F6HP
• Description: 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES
• Manufacturer: RENESAS [Renesas Technology Corp]

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Table 14.18 SIM Mode Specifications
NOTES:
J
6
0
14.1.6 Special Mode 4 (SIM Mode) (UART2)
Transfer data format
Transfer clock
Transmission start condition
Reception start condition
Error detection
C
Interrupt request
generation timing
2
9
Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be
implemented, and this mode allows output of a low from the TxD2 pin when a parity error is detected.
Table 14.18 lists the specifications of SIM mode. Table 14.19 lists the registers used in the SIM mode
and the register values set.
0 .
2 /
B
1. If an overrun error occurs, bits 8 to 0 in the U2RB register are undefined. The IR bit in the S2RIC
2. A transmit interrupt request is generated by setting the U2IRS bit in the U2C1 register to “1” (trans-
0
0
8
0
register remains unchanged.
mission complete) and U2ERE bit to “1” (error signal output) after reset. Therefore, when using
SIM mode, be sure to clear the IR bit to “0” (no interrupt request) after setting these bits.
4
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J
7
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0 -
. n
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Item
2
3
p
0
, 1
0
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2
0
1
0
6
(2)
7
C
2 /
page 207
, 8
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1
6
• Direct format
• Inverse format
• The CKDIR bit in the U2MR register is set to “0” (internal clock) : fi/ (16(n+1))
• The CKDIR bit is set to “1” (external clock
• Before transmission can start, the following requirements must be met
_
_
• Before reception can start, the following requirements must be met
_
_
• For transmission
• For reception
• Overrun error
• Framing error
• Parity error
• Error sum flag
C
During transmission, a parity error is detected by the level of input to the R
fi = f
f
When the serial I/O finished sending data from the U2TB transfer register (U2IRS bit ="1")
When transferring data from the UART2 receive register to the U2RB register (at
completion of reception)
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the bit one before the last stop bit in the the next data
This error occurs when the number of stop bits set is not detected
During reception, if a parity error is detected, parity error signal is output from the
TxD
when a transmission interrupt occurs
This flag is set to "1" when any of the overrun, framing, and parity errors is encountered
The TE bit in the U2C1 register is set to "1" (transmission enabled)
The TI bit in the U2C1 register is set to "0" (data present in U2TB register)
The RE bit in the U2C1 register is set to "1" (reception enabled)
Start bit detection
EXT
f o
2 /
8
3
: Input from CLK
2
1SIO
) B
8
pin.
5
, f
2SIO
(1)
, f
8SIO
, f
2
32SIO
pin.
. n: Setting value of U2BRG register
n: Setting value of U2BRG register
Specification
) : f
EXT
/16(n+1)
00
00
16
16
to FF
to FF
14. Serial I/O
X
D
16
2
16
pin